Rapid acquisition spreading codes for spread-spectrum communications

ABSTRACT

A method and system for rapidly acquiring a spreading code, used in a code division multiple access (CDMA) system. A first long code and a second long code, with each long code having a length of N chips, are generated. The first long code is different from the second long code. The first long code and the second long code are transmitted at a first phase angle and at a second phase angle, respectively, on a carrier signal, over a communications channel using radio waves. The first long code and the second long code may be transmitted at an in-phase (I) angle and at a quadrature-phase (Q) angle, respectively, on the carrier signal. From the communications channel, an I-phase acquisition circuit and a Q-phase acquisition circuit may acquire, in parallel, the first long code and the second long code from the I-phase angle and the Q-phase angle, respectively, of the carrier signal by searching, in parallel, N/2 chips, the first long code and the second long code.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.09/757,768 filed on Jan. 10, 2001, which is a continuation of U.S.application Ser. No. 08/956,980 filed on Oct. 23, 1997, which issued onApr. 3, 2001 as U.S. Pat. No. 6,212,174; which is a division of U.S.application Ser. No. 08/669,775 filed on Jun. 27, 1996, which issued asU.S. Pat. No. 5,799,010 on Aug. 25, 1998, which claims priority fromU.S. Provisional Application No. 60/000,775 filed on Jun. 30, 1995.

FIELD OF INVENTION

The present invention generally pertains to Code Division MultipleAccess (CDMA) communications, also known as spread-spectrumcommunications. More particularly, the present invention pertains to asystem and method for providing a high capacity, CDMA communicationssystem which provides for one or more simultaneous user bearer channelsover a given radio frequency, allowing dynamic allocation of bearerchannel rate while rejecting multipath interference.

BACKGROUND

Providing quality telecommunication services to user groups which areclassified as remote, such as rural telephone systems and telephonesystems in underdeveloped countries, has proven to be a challenge inrecent years. These needs have been partially satisfied by wirelessradio services, such as fixed or mobile frequency division multiplex(FDM) systems, frequency division multiple access (FDMA) systems, timedivision multiplex (TDM) systems, time division multiple access (TDMA)systems, combination frequency and time division (FD/TDMA) systems, andother land mobile radio systems. Usually, these remote services arefaced with more potential users than can be supported simultaneously bytheir frequency or spectral bandwidth capacity.

Recognizing these limitations, recent advances in wirelesscommunications have used spread spectrum modulation techniques toprovide simultaneous communication by multiple users. Spread spectrummodulation refers to modulating an information signal with a spreadingcode signal; the spreading code signal being generated by a codegenerator where the period Tc of the spreading code is substantiallyless than the period of the information data bit or symbol signal. Thecode may modulate the carrier frequency upon which the information hasbeen sent, called frequency-hopped spreading, or may directly modulatethe signal by multiplying the spreading code with the information datasignal, called direct-sequence (DS) spreading. Spread-spectrummodulation produces a signal with bandwidth substantially greater thanthat required to transmit the information signal. Synchronous receptionand despreading of the signal at the receiver recovers the originalinformation. A synchronous demodulator in the receiver uses a referencesignal to synchronize the despreading circuits to the inputspread-spectrum modulated signal to recover the carrier and informationsignals. The reference signal can be a spreading code which is notmodulated by an information signal. Such use of a synchronousspread-spectrum modulation and demodulation for wireless communicationis described in U.S. Pat. No. 5,228,056 entitled SYNCHRONOUSSPREAD-SPECTRUM COMMUNICATIONS SYSTEM AND METHOD by Donald L. Schilling,which techniques are incorporated herein by reference.

Spread-spectrum modulation in wireless networks offers many advantagesbecause multiple users may use the same frequency band with minimalinterference to each user's receiver. Spread-spectrum modulation alsoreduces effects from other sources of interference. In addition,synchronous spread-spectrum modulation and demodulation techniques maybe expanded by providing multiple message channels for a single user,each spread with a different spreading code, while still transmittingonly a single reference signal to the user. Such use of multiple messagechannels modulated by a family of spreading codes synchronized to apilot spreading code for wireless communication is described in U.S.Pat. No. 5,166,951 entitled HIGH CAPACITY SPREAD-SPECTRUM CHANNEL byDonald L. Schilling, which is incorporated herein by reference.

One area in which spread-spectrum techniques are used is in the field ofmobile cellular communications to provide personal communicationservices (PCS). Such systems desirably support large numbers of users,control Doppler shift and fade, and provide high speed digital datasignals with low bit error rates. These systems employ a family oforthogonal or quasi-orthogonal spreading codes, with a pilot spreadingcode sequence synchronized to the family of codes. Each user is assignedone of the spreading codes as a spreading function. Related problems ofsuch a system are: supporting a large number of users with theorthogonal codes, handling reduced power available to remote units, andhandling multipath fading effects. Solutions to such problems includeusing phased-array antennas to generate multiple steerable beams andusing very long orthogonal or quasi-orthogonal code sequences. Thesesequences may be reused by cyclic shifting of the code synchronized to acentral reference and diversity combining of multipath signals. Suchproblems associated with spread spectrum communications, and methods toincrease the capacity of a multiple access, spread-spectrum system aredescribed in U.S. Pat. No. 4,901,307 entitled “Spread Spectrum MultipleAccess Communication System Using Satellite or Terrestrial Repeaters” byGilhousen et al., which is incorporated herein by reference.

The problems associated with the prior art systems focus around reliablereception and synchronization of the receiver despreading circuits tothe received signal. The presence of multipath fading introduces aparticular problem with spread spectrum receivers in that a receivermust somehow track the multipath components to maintain code-phase lockof the receiver's despreading means with the input signal. Prior artreceivers generally track only one or two of the multipath signals, butthis method is not satisfactory because the combined group of low powermultipath signal components may actually contain far more power than theone or two strongest multipath components. The prior art receivers trackand combine the strongest components to maintain a predetermined biterror rate (BER) of the receiver. Such a receiver is described, forexample, in U.S. Pat. No. 5,109,390 entitled “Diversity Receiver in aCDMA Cellular Telephone System” by Gilhousen et al., which isincorporated herein by reference. A receiver that combines all multipathcomponents, however, is able to maintain the desired BER with a signalpower that is lower than that of prior art systems because more signalpower is available to the receiver. Consequently, there is a need for aspread spectrum communication system employing a receiver that trackssubstantially all of the multipath signal components, so thatsubstantially all multipath signals may be combined in the receiver, andhence the required transmit power of the signal for a given BER may bereduced.

Another problem associated with multiple access, spread-spectrumcommunication systems is the need to reduce the total transmitted powerof users in the system, since users may have limited available power. Anassociated problem requiring power control in spread-spectrum systems isrelated to the inherent characteristic of spread-spectrum systems thatone user's spread-spectrum signal is received by another user's receiveras noise with a certain power level. Consequently, users transmittingwith high levels of signal power may interfere with other users'reception. Also, if a user moves relative to another user's geographiclocation, signal fading and distortion require that the users adjusttheir transmit power level to maintain a particular signal quality. Atthe same time, the system should keep the power that the base stationreceives from all users relatively constant. Finally, because it ispossible for the spread-spectrum system to have more remote users thancan be supported simultaneously, the power control system should alsoemploy a capacity management method which rejects additional users whenthe maximum system power level is reached.

Prior spread-spectrum systems have employed a base station that measuresa received signal and sends an adaptive power control (APC) signal tothe remote users. Remote users include a transmitter with an automaticgain control (AGC) circuit which responds to the APC signal. In suchsystems the base station monitors the overall system power or the powerreceived from each user, and sets the APC signal accordingly. Such aspread-spectrum power control system and method is described in U.S.Pat. No. 5,299,226 entitled “Adaptive Power Control for a SpreadSpectrum Communications System and Method,” and U.S. Pat. No. 5,093,840entitled “Adaptive Power Control for a Spread Spectrum Transmitter”,both by Donald L. Schilling and incorporated herein by reference. Thisopen loop system performance may be improved by including a measurementof the signal power received by the remote user from the base station,and transmitting an APC signal back to the base station to effectuate aclosed loop power control method. Such closed loop power control isdescribed, for example, in U.S. Pat. No. 5,107,225 entitled “HighDynamic Range Closed Loop Automatic Gain Control Circuit” by Wheatley,III et al., which is incorporated herein by reference.

These power control systems, however, exhibit several disadvantages.First, the base station must perform complex power control algorithms,increasing the amount of processing in the base station. Second, thesystem actually experiences several types of power variation: variationin the noise power caused by the variation in the number of users andvariations in the received signal power of a particular bearer channel.These variations occur with different frequency, so simple power controlalgorithms can be optimized to compensate for only one of the two typesof variation. Finally, these power algorithms tend to drive the overallsystem power to a relatively high level. Consequently, there is a needfor a spread-spectrum power control method that rapidly responds tochanges in bearer channel power levels, while simultaneously makingadjustments to all users' transmit power in response to changes in thenumber of users. Also, there is a need for an improved spread-spectrumcommunication system employing a closed loop power control system whichminimizes the system's overall power requirements while maintaining asufficient BER at the individual remote receivers. In addition, such asystem should control the initial transmit power level of a remote userand manage total system capacity.

Spread-spectrum communication systems desirably should support largenumbers of users, each of which has at least one communication channel.In addition, such a system should provide multiple generic informationchannels to broadcast information to all users and to enable users togain access to the system. Using prior art spread-spectrum systems thiscould only be accomplished by generating large numbers of spreading codesequences.

Further, spread-spectrum systems should use sequences that areorthogonal or nearly orthogonal to reduce the probability that areceiver locks to the wrong spreading code sequence or phase. The use ofsuch orthogonal codes and the benefits arising therefrom are outlined inU.S. Pat. No. 5,103,459 entitled “System and Method for GeneratingSignal Waveforms in a CDMA Cellular Telephone System” by Gilhousen etal., and U.S. Pat. No. 5,193,094 entitled “Method and Apparatus forGenerating Super-Orthogonal Convolutional Codes and the DecodingThereof” by Andrew J. Viterbi, both of which are incorporated herein byreference. However, generating such large families of code sequenceswith such properties is difficult. Also, generating large code familiesrequires generating sequences which have a long period beforerepetition. Consequently, the time a receiver takes to achievesynchronization with such a long sequence is increased. Prior artspreading code generators often combine shorter sequences to make longersequences, but such sequences may no longer be sufficiently orthogonal.Therefore, there is a need for an improved method for reliablygenerating large families of code sequences that exhibit nearlyorthogonal characteristics and have a long period before repetition, butalso include the benefit of a short code sequence that reduces the timeto acquire and lock the receiver to the correct code phase. In addition,the code generation method should allow generation of codes with anyperiod, since the spreading code period is often determined byparameters used such as data rate or frame size.

Another desirable characteristic of spreading code sequences is that thetransition of the user data values occurs at a transition of the codesequence values. Since data typically has a period which is divisible by2^(N), such a characteristic usually requires the code-sequence to be aneven length of 2^(N). However, code generators, as is well known in theart, generally use linear feedback shift registers which generate codesof length 2^(N)−1. Some generators include a method to augment thegenerated code sequence by inserting an additional code value, asdescribed, for example, in U.S. Pat. No. 5,228,054 entitled“Power-of-Two Length Pseudo-Noise Sequence Generator With Fast OffsetAdjustment” by Rueth et al., which is incorporated herein by reference.Consequently, the spread-spectrum communication system should alsogenerate spreading code sequences of even length.

Finally, the spread-spectrum communication system should be able tohandle many different types of data, such as FAX, voiceband data andISDN, in addition to traditional voice traffic. To increase the numberof users supported, many systems employ encoding techniques such asADPCM to achieve “compression” of the digital telephone signal. FAX,ISDN and other data, however, require the channel to be a clear channel.Consequently, there is a need for a spread spectrum communication systemthat supports compression techniques that also dynamically modify thespread spectrum bearer channel between an encoded channel and a clearchannel in response to the type of information contained in the user'ssignal.

SUMMARY

The present invention is embodied in a multiple access, spread spectrumcommunication system which processes a plurality of information signalsreceived simultaneously over telecommunication lines for simultaneoustransmission over a radio frequency (RF) channel as acode-division-multiplexed (CDM) signal. The system includes a radiocarrier station (RCS) which receives a call request signal thatcorresponds to a telecommunication line information signal, and a useridentification signal that identifies a user to which the call requestand information signal are addressed. The receiving apparatus is coupledto a plurality of code division multiple access (CDMA) modems, one ofwhich provides a global pilot code signal and a plurality of messagecode signals, and each of the CDMA modems combines one of the pluralityof information signals with its respective message code signal toprovide a spread-spectrum processed signal. The plurality of messagecode signals of the plurality of CDMA modems are synchronized to theglobal pilot code signal. The system also includes assignment apparatusthat is responsive to a channel assignment signal for coupling therespective information signals received on the telecommunication linesto indicated ones of the plurality of modems. The assignment apparatusis coupled to a time-slot exchange means. The system further includes asystem channel controller coupled to a remote call-processor and to thetime-slot exchange means. The system channel controller is responsive tothe user identification signal, to provide the channel assignmentsignal. In the system, an RF transmitter is connected to all of themodems to combine the plurality of spread-spectrum processed messagesignals with the global pilot code signal to generate a CDM signal. TheRF transmitter also modulates a carrier signal with the CDM signal andtransmits the modulated carrier signal through an RF communicationchannel.

The transmitted CDM signal is received from the RF communication channelby a subscriber unit (SU) which processes and reconstructs thetransmitted information signal assigned to the subscriber. The SUincludes a receiving means for receiving and demodulating the CDM signalfrom the carrier. In addition, the SU comprises a subscriber unitcontroller and a CDMA modem which includes a processing means foracquiring the global pilot code and despreading the spread-spectrumprocessed signal to reconstruct the transmitted information signal.

The RCS and the SUs each contain CDMA modems for transmission andreception of telecommunication signals including information signals andconnection control signals. The CDMA modem comprises a modem transmitterhaving: a code generator for providing an associated pilot code signaland for generating a plurality of message code signals; a spreadingmeans for combining each of the information signals with a respectiveone of the message code signals to generate spread-spectrum processedmessage signals; and a global pilot code generator which provides aglobal pilot code signal to which the message code signals aresynchronized.

The CDMA modem also comprises a modem receiver having associated pilotcode acquisition and tracking logic. The associated pilot codeacquisition logic includes an associated pilot code generator; a groupof associated pilot code correlators for correlating code-phase delayedversions of the associated pilot signal with a receive CDM signal forproducing a despread associated pilot signal. The code phase of theassociated pilot signal is changed responsive to an acquisition signalvalue until a detector indicates the presence of the despread associatedpilot code signal by changing the acquisition signal value. Theassociated pilot code signal is synchronized to the global pilot signal.The associated pilot code tracking logic adjusts the associated pilotcode signal in phase responsive to the acquisition signal so that thesignal power level of the despread associated pilot code signal ismaximized. Finally, the CDMA modem receiver includes a group of messagesignal acquisition circuits. Each message signal acquisition circuitincludes a plurality of receive message signal correlators forcorrelating one of the local receive message code signals with the CDMsignal to produce a respective despread receive message signal.

To generate large families of nearly mutually orthogonal codes used bythe CDMA modems, the present invention includes a code sequencegenerator. The code sequences are assigned to a respective logicalchannel of the spread-spectrum communication system, which includesIn-phase (I) and Quadrature (Q) transmission over RF communicationchannels. One set of sequences is used as pilot sequences which are codesequences transmitted without modulation by a data signal. The codesequence generator circuit includes a long code sequence generatorincluding a linear feedback shift register, a memory which provides ashort, even code sequence, and a plurality of cyclic shift, feedforwardsections which provide other members of the code family which exhibitminimal correlation with the code sequence applied to the feedforwardcircuit. The code sequence generator further includes a group of codesequence combiners for combining each phase shifted version of the longcode sequence with the short, even code sequence to produce a group, orfamily, of nearly mutually orthogonal codes.

Further, the present invention includes several methods for efficientutilization of the spread-spectrum channels. First, the system includesa bearer channel modification system which comprises a group of messagechannels between a first transceiver and second transceiver. Each of thegroup of message channels supports a different information signaltransmission rate. The first transceiver monitors a received informationsignal to determine the type of information signal that is received, andproduces a coding signal relating to the coding signal. If a certaintype of information signal is present, the first transceiver switchestransmission from a first message channel to a second message channel tosupport the different transmission rate. The coding signal istransmitted by the first transceiver to the second transceiver, and thesecond transceiver switches to the second message channel to receive theinformation signal at a different transmission rate.

Another method to increase efficient utilization of the bearer messagechannels is the method of idle-code suppression used by the presentinvention. The spread-spectrum transceiver receives a digital datainformation signal including a predetermined flag pattern correspondingto an idle period. The method includes the steps of: 1) delaying andmonitoring the digital data signal; 2) detecting the predetermined flagpattern; 3) suspending transmission of the digital data signal when theflag pattern is detected; and 4) transmitting the data signal as aspread-spectrum signal when the flag pattern is not detected.

The present invention includes a system and method for closed loop APCfor the RCS and SUs of the spread-spectrum communication system. The SUstransmit spread-spectrum signals, the RCS acquires the spread-spectrumsignals, and the RCS detects the received power level of thespread-spectrum signals plus any interfering signal including noise. TheAPC system includes the RCS and a plurality of SUs, wherein the RCStransmits a plurality of forward channel information signals to the SUsas a plurality of forward channel spread-spectrum signals having arespective forward transmit power level, and each SU transmits to thebase station at least one reverse spread-spectrum signal having arespective reverse transmit power level and at least one reverse channelspread-spectrum signal which includes a reverse channel informationsignal.

The APC system includes an adaptive forward power control (AFPC) system,and an adaptive reverse power control (ARPC) system. The AFPC systemoperates by measuring, at the SU, a forward signal-to-noise ratio of therespective forward channel information signal, generating a respectiveforward channel error signal corresponding to a forward error betweenthe respective forward signal-to-noise ratio and a pre-determinedsignal-to-noise value, and transmitting the respective forward channelerror signal as part of a respective reverse channel information signalfrom the SU to the RCS. The RCS includes a plural number of AFPCreceivers for receiving the reverse channel information signals andextracting the forward channel error signals from the respective reversechannel information signals. The RCS also adjusts the respective forwardtransmit power level of each one of the respective forwardspread-spectrum signals responsive to the respective forward errorsignal.

The ARPC system operates by measuring, in the RCS, a reversesignal-to-noise ratio of each of the respective reverse channelinformation signals, generating a respective reverse channel errorsignal representing an error between the respective reverse channelsignal-to-noise ratio and a respective pre-determined signal-to-noisevalue, and transmitting the respective reverse channel error signal as apart of a respective forward channel information signal to the SU. EachSU includes an ARPC receiver for receiving the forward channelinformation signal and extracting the respective reverse error signalfrom the forward channel information signal. The SU adjusts the reversetransmit power level of the respective reverse spread-spectrum signalresponsive to the respective reverse error signal.

BRIEF DESCRIPTION OF THE DRAWING(S)

FIG. 1 is a block diagram of a code division multiple accesscommunication system according to the present invention.

FIG. 2 a is a block diagram of a 36 stage linear shift register suitablefor use with long spreading code of the code generator of the presentinvention.

FIG. 2 b is a block diagram of circuitry which illustrates thefeed-forward operation of the code generator.

FIG. 2 c is a block diagram of an exemplary code generator of thepresent invention including circuitry for generating spreading codesequences from the long spreading codes and the short spreading codes.

FIG. 2 d is an alternate embodiment of the code generator circuitincluding delay elements to compensate for electrical circuit delays.

FIG. 3 a is a graph of the constellation points of the pilot spreadingcode QPSK signal.

FIG. 3 b is a graph of the constellation points of the message channelQPSK signal.

FIG. 3 c is a block diagram of exemplary circuitry which implements themethod of tracking the received spreading code phase of the presentinvention.

FIG. 4 is a block diagram of the tracking circuit that tracks the medianof the received multipath signal components.

FIG. 5 a is a block diagram of the tracking circuit that tracks thecentroid of the received multipath signal components.

FIG. 5 b is a block diagram of the Adaptive Vector Correlator.

FIG. 6 is a block diagram of exemplary circuitry which implements theacquisition decision method of the correct spreading code phase of thereceived pilot code of the present invention.

FIG. 7 is a block diagram of an exemplary pilot rake filter whichincludes the tracking circuit and digital phase locked loop fordespreading the pilot spreading code, and generator of the weightingfactors of the present invention.

FIG. 8 a is a block diagram of an exemplary adaptive vector correlatorand matched filter for despreading and combining the multipathcomponents of the present invention.

FIG. 8 b is a block diagram of an alternative implementation of theadaptive vector correlator and adaptive matched filter for despreadingand combining the multipath components of the present invention.

FIG. 8 c is a block diagram of an alternative embodiment of the adaptivevector correlator and adaptive matched filter for despreading andcombining the multipath components of the present invention.

FIG. 8 d is a block diagram of the Adaptive Matched Filter of oneembodiment of the present invention.

FIG. 9 is a block diagram of the elements of an exemplary radio carrierstation (RCS) of the present invention.

FIG. 10 is a block diagram of the elements of an exemplary multiplexersuitable for use in the RCS shown in FIG. 9.

FIG. 11 is a block diagram of the elements of an exemplary wirelessaccess controller (WAC) of the RCS shown in FIG. 9.

FIG. 12 is a block diagram of the elements of an exemplary modeminterface unit (MIU) of the RCS shown in FIG. 9.

FIG. 13 is a high level block diagram showing the transmit, receive,control and code generation circuitry of the CDMA modem.

FIG. 14 is a block diagram of the transmit section of the CDMA modem.

FIG. 15 is a block diagram of an exemplary modem input signal receiver.

FIG. 16 is a block diagram of an exemplary convolutional encoder as usedin the present invention.

FIG. 17 is a block diagram of the receive section of the CDMA modem.

FIG. 18 is a block diagram of an exemplary adaptive matched filter asused in the CDMA modem receive section.

FIG. 19 is a block diagram of an exemplary pilot rake as used in theCDMA modem receive section.

FIG. 20 is a block diagram of an exemplary auxiliary pilot rake as usedin the CDMA modem receive section.

FIG. 21 is a block diagram of an exemplary video distribution circuit(VDC) of the RCS shown in FIG. 9.

FIG. 22 is a block diagram of an exemplary RF transmitter/receiver andexemplary power amplifiers of the RCS shown in FIG. 9.

FIG. 23 is a block diagram of an exemplary SU of the present invention.

FIG. 24 is a flow-chart diagram of an exemplary call establishmentalgorithm for an incoming call request used by the present invention forestablishing a bearer channel between an RCS and an SU.

FIG. 25 is a flow-chart diagram of an exemplary call establishmentalgorithm for an outgoing call request used by the present invention forestablishing a bearer channel between an RCS and an SU.

FIG. 26 is a flow-chart diagram of an exemplary maintenance powercontrol algorithm of the present invention.

FIG. 27 is a flow-chart diagram of an exemplary AFPC algorithm of thepresent invention.

FIG. 28 is a flow-chart diagram of an exemplary ARPC algorithm of thepresent invention.

FIGS. 29A and 29B, taken together, are a block diagram of an exemplaryclosed loop power control system of the present invention when thebearer channel is established.

FIGS. 30A and 30B, taken together, are a block diagram of an exemplaryclosed loop power control system of the present invention during theprocess of establishing the bearer channel.

GLOSSARY OF ACRONYMS

Acronym Definition

-   -   AC Assigned Channels    -   A/D Analog-to-Digital    -   ADPCM Adaptive Differential Pulse Code Modulation    -   AFPC Adaptive Forward Power Control    -   AGC Automatic Gain Control    -   AMF Adaptive Matched Filter    -   APC Adaptive Power Control    -   ARPC Adaptive Reverse Power Control    -   ASPT Assigned Pilot    -   AVC Adaptive Vector Correlator    -   AXCH Access Channel    -   B-CDMA Broadband Code Division Multiple Access    -   BCM Bearer Channel Modification    -   BER Bit Error Rate    -   BS Base Station    -   CC Call Control    -   CDM Code Division Multiplex    -   CDMA Code Division Multiple Access    -   CLK Clock Signal Generator    -   CO Central Office    -   CTCH Control Channel    -   CUCH Check-Up Channel    -   dB Decibels    -   DCC Data Combiner Circuitry    -   DI Distribution Interface    -   DLL Delay Locked Loop    -   DM Delta Modulator    -   DS Direct Sequence    -   EPIC Extended PCM Interface Controller    -   FBCH Fast Broadcast Channel    -   FDM Frequency Division Multiplex    -   FD/TDMA Frequency & Time Division Systems    -   FDMA Frequency Division Multiple Access    -   FEC Forward Error Correction    -   FSK Frequency Shift Keying    -   FSU Fixed Subscriber Unit    -   GC Global Channel    -   GLPT Global Pilot    -   GPC Global Pilot Code    -   GPSK Gaussian Phase Shift Keying    -   GPS Global Positioning System    -   HPPC High Power Passive Components    -   HSB High Speed Bus    -   I In-Phase    -   IC Interface Controller    -   ISDN Integrated Services Digital Network    -   ISST Initial System Signal Threshold    -   LAXPT Long Access Pilot    -   LAPD Link Access Protocol    -   LCT Local Craft Terminal    -   LE Local Exchange    -   LFSR Linear Feedback Shift Register    -   LI Line Interface    -   LMS Least Mean Square    -   LOL Loss of Lock    -   LPF Low Pass Filter    -   LSR Linear Shift Register    -   MISR Modem Input Signal Receiver    -   MIU Modem Interface Unit    -   MM Mobility Management    -   MOI Modem Output Interface    -   MPC Maintenance Power Control    -   MPSK M-ary Phase Shift Keying    -   MSK Minimum Shift Keying    -   MSU Mobile Subscriber Unit    -   NE Network Element    -   OMS Operation and Maintenance System    -   OS Operations System    -   OQPSK Offset Quadrature Phase Shift Keying    -   OW Order Wire    -   PARK Portable Access Rights Key    -   PBX Private Branch Exchange    -   PCM Pulse Coded Modulation    -   PCS Personal Communication Services    -   PG Pilot Generator    -   PLL Phase Locked Loop    -   PLT Pilot    -   PN Pseudonoise    -   POTS Plain Old Telephone Service    -   PSTN Public Switched Telephone Network    -   Q Quadrature    -   QPSK Quadrature Phase Shift Keying    -   RAM Random Access Memory    -   RCS Radio Carrier Station    -   RDI Receiver Data Input Circuit    -   RDU Radio Distribution Unit    -   RF Radio Frequency    -   RLL Radio Local Loop    -   SAXPT Short Access Channel Pilots    -   SBCH Slow Broadcast Channel    -   SHF Super High Frequency    -   SIR Signal Power to Interface Noise Power Ratio    -   SLIC Subscriber Line Interface Circuit    -   SNR Signal-to-Noise Ratio    -   SPC Service PC    -   SPRT Sequential Probability Ratio Test    -   STCH Status Channel    -   SU Subscriber Unit    -   TDM Time Division Multiplexing    -   TMN Telecommunication Management Network    -   TRCH Traffic Channels    -   TSI Time-Slot Interchanger    -   TX Transmit    -   TXIDAT I-Modem Transmit Data Signal    -   TXQDAT Q-Modem Transmit Data Signal    -   UHF Ultra High Frequency    -   VCO Voltage Controlled Oscillator    -   VDC Video Distribution Circuit    -   VGA Variable Gain Amplifier    -   VHF Very High Frequency    -   WAC Wireless Access Controller

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

I. General System Description

The system of the present invention provides local-loop telephoneservice using radio links between one or more base stations and multipleremote subscriber units. In the exemplary embodiment, a radio link isdescribed for a base station communicating with a fixed subscriber unit(FSU), but the system is equally applicable to systems includingmultiple base stations with radio links to both FSUs and mobilesubscriber units (MSUs). Consequently, the remote subscriber units arereferred to herein as subscriber units (SUs).

Referring to FIG. 1, base station (BS) 101 provides call connection to alocal exchange (LE) 103 or any other telephone network switchinginterface, such as a private branch exchange (PBX) and includes a radiocarrier station (RCS) 104. One or more RCSs 104, 105, 110 connect to aradio distribution unit (RDU) 102 through links 131, 132, 137, 138, 139,and RDU 102 interfaces with LE 103 by transmitting and receiving callset-up, control, and information signals through telco links 141, 142,150. SUs 116, 119 communicate with the RCS 104 through radio links 161,162, 163, 164, 165. Alternatively, another embodiment of the inventionincludes several SUs and a “master” SU with functionality similar to theRCS 104. Such an embodiment may or may not have connection to a localtelephone network.

The radio links 161 to 165 operate within the frequency bands of theDCS1800 standard (1.71-1.785 GHz and 1.805-1.880 GHz); the US-PCSstandard (1.85-1.99 GHz); and the CEPT standard (2.0-2.7 GHz). Althoughthese bands are used in the described embodiment, the invention isequally applicable to the entire UHF to SHF bands, including bands from2.7 GHz to 5 GHz. The transmit and receive bandwidths are multiples of3.5 MHz starting at 7 MHz, and multiples of 5 MHz starting at 10 MHz,respectively. The described system includes bandwidths of 7, 10, 10.5,14 and 15 MHz. In the exemplary embodiment of the invention, the minimumguard band between the uplink and downlink is 20 MHz, and is desirablyat least three times the signal bandwidth. The duplex separation isbetween 50 to 175 MHz, with the described invention using 50, 75, 80,95, and 175 MHz. Other frequencies may also be used.

Although the described embodiment uses different spread-spectrumbandwidths centered around a carrier for the transmit and receivespread-spectrum channels, the present method is readily extended tosystems using multiple spread-spectrum bandwidths for the transmitchannels and multiple spread-spectrum bandwidths for the receivechannels. Alternatively, because spread-spectrum communication systemshave the inherent feature that one user's transmission appears as noiseto another user's despreading receiver, an embodiment may employ thesame spread-spectrum channel for both the transmit and receive pathchannels. In other words, uplink and downlink transmissions can occupythe same frequency band. Furthermore, the present method may be readilyextended to multiple CDMA frequency bands, each conveying a respectivelydifferent set of messages, uplink, downlink or uplink and downlink.

The spread binary symbol information is transmitted over the radio links161 to 165 using quadrature phase shift keying (QPSK) modulation withNyquist Pulse Shaping in the present embodiment, although othermodulation techniques may be used, including, but not limited to, offsetQPSK (OQPSK), minimum shift keying (MSK), Gaussian phase shift keying(GPSK) and M-ary phase shift keying (MPSK).

The radio links 161 to 165 incorporate Broadband Code Division MultipleAccess (B-CDMA™) as the mode of transmission in both the uplink anddownlink directions. CDMA (also known as spread spectrum) communicationtechniques used in multiple access systems are well-known, and aredescribed in U.S. Pat. No. 5,228,056 entitled “SynchronousSpread-Spectrum Communications System and Method” by Donald T.Schilling. The system described utilizes the direct sequence (DS)spreading technique. The CDMA modulator performs the spread-spectrumspreading code sequence generation, which can be a pseudonoise (PN)sequence; and complex DS modulation of the QPSK signals with spreadingcode sequences for the in-phase (I) and quadrature (Q) channels. Pilotsignals are generated and transmitted with the modulated signals, andpilot signals of the present embodiment are spreading codes notmodulated by data. The pilot signals are used for synchronization,carrier phase recovery and for estimating the impulse response of theradio channel. Each SU includes a single pilot generator and at leastone CDMA modulator and demodulator, together known as a CDMA modem. EachRCS 104, 105, 110 has a single pilot generator plus sufficient CDMAmodulators and demodulators for all of the logical channels in use byall SUs.

The CDMA demodulator despreads the signal with appropriate processing tocombat or exploit multipath propagation effects. Parameters concerningthe received power level are used to generate the APC information which,in turn, is transmitted to the other end of the communication link. TheAPC information is used to control transmit power of the AFPC and ARPClinks. In addition, each RCS 104, 105 and 110 can perform maintenancepower control (MPC), in a manner similar to APC, to adjust the initialtransmit power of each SU 111, 112, 115, 117 and 118. Demodulation iscoherent where the pilot signal provides the phase reference.

The described radio links support multiple traffic channels with datarates of 8, 16, 32, 64, 128, and 144 kb/s. The physical channel to whicha traffic channel is connected operates with a 64 k symbol/sec rate.Other data rates may be supported, and forward error correction (FEC)coding can be employed. For the described embodiment, FEC with codingrate of ½ and constraint length 7 is used. Other rates and constraintlengths can be used consistent with the code generation techniquesemployed.

Diversity combining at the radio antennas of RCS 104, 105 and 110 is notnecessary because CDMA has inherent frequency diversity due to thespread bandwidth. Receivers include adaptive matched filters (AMFs) (notshown in FIG. 1) which combine the multipath signals. In the presentembodiment, the exemplary AMFs perform maximal ratio combining.

Referring to FIG. 1, RCS 104 interfaces to RDU 102 through links 131,132, 137 with, for example, 1.544 Mb/s DS1, 2.048 Mb/s E1; or HDSLformats to receive and send digital data signals. While these aretypical telephone company standardized interfaces, the present inventionis not limited to these digital data formats only. The exemplary RCSline interface (not shown in FIG. 1) translates the line coding (such asHDB3, B8ZS, AMI) and extracts or produces framing information, performsalarms and facility signaling functions, as well as channel specificloop-back and parity check functions. The interfaces for thisdescription provide 64 kb/s PCM encoded or 32 kb/s ADPCM encodedtelephone traffic channels or ISDN channels to the RCS for processing.Other ADPCM encoding techniques can be used consistent with the sequencegeneration techniques.

The system of the present invention also supports bearer ratemodification between the RCS 104 and each SU 111, 112, 115, 117 and 118communicating with the RCS 104 in which a CDMA message channelsupporting 64 kb/s may be assigned to voiceband data or FAX when ratesabove 4.8 kb/s are present. Such 64 kb/s bearer channel is considered anunencoded channel. For ISDN, bearer rate modification may be donedynamically, based upon the D channel messages.

In FIG. 1, each SU 111, 112, 115, 117 and 118 either includes orinterfaces with a telephone unit 170, or interfaces with a local switch(PBX) 171. The input from the telephone unit may include voice,voiceband data and signaling. The SU translates the analog signals intodigital sequences, and may also include a data terminal 172 or an ISDNinterface 173. The SU can differentiate voice input, voiceband data orFAX and digital data. The SU encodes voice data with techniques such asADPCM at 32 kb/s or lower rates, and detects voiceband data or FAX withrates above 4.8 kb/s to modify the traffic channel (bearer ratemodification) for unencoded transmission. Also, A-law, u-law or nocompanding of the signal may be performed before transmission. Fordigital data, data compression techniques, such as idle flag removal,may also be used to conserve capacity and minimize interference.

The transmit power levels of the radio interface between RCS 104 and SUs111, 112, 115, 117 and 118 are controlled using two different closedloop power control methods. The AFPC method determines the downlinktransmit power level, and the ARPC method determines the uplink transmitpower level. The logical control channel by which SU 111 and RCS 104,for example, transfer power control information operates at least a 16kHz update rate. Other embodiments may use a faster or slower updaterate, for example 64 kHz. These algorithms ensure that the transmitpower of a user maintains an acceptable bit-error rate (BER), maintainsthe system power at a minimum to conserve power and maintains the powerlevel of all SUs 111, 112, 115, 117 and 118 received by RCS 104 at anearly equal level.

In addition, the system uses an optional maintenance power controlmethod during the inactive mode of a SU. When SU 111 is inactive orpowered-down to conserve power, the unit occasionally activates toadjust its initial transmit power level setting in response to amaintenance power control signal from RCS 104. The maintenance powersignal is determined by the RCS 104 by measuring the received powerlevel of SU 111 and present system power level and, from this,calculates the necessary initial transmit power. The method shortens thechannel acquisition time of SU 111 to begin a communication. The methodalso prevents the transmit power level of SU 111 from becoming too highand interfering with other channels during the initial transmissionbefore the closed loop power control reduces the transmit power.

RCS 104 obtains synchronization of its clock from an interface line suchas, but not limited to, E1, T1, or HDSL interfaces. RCS 104 can alsogenerate its own internal clock signal from an oscillator which may beregulated by a global positioning system (GPS) receiver. RCS 104generates a global pilot code, a channel with a spreading code but nodata modulation, which can be acquired by remote SUs 111 through 118.All transmission channels of the RCS are synchronized to the pilotchannel, and spreading code phases of code generators (not shown) usedfor logical communication channels within RCS 104 are also synchronizedto the pilot channel's spreading code phase. Similarly, SUs 111 through118 which receive the global pilot code of RCS 104 synchronize thespreading and de-spreading code phases of the code generators (notshown) of the SUs to the global pilot code.

RCS 104, SU 111 and RDU 102 may incorporate system redundancy of systemelements and automatic switching between internal functional systemelements upon a failure event to prevent loss or drop-out of a radiolink, power supply, traffic channel or group of traffic channels.

II. Logical Communication Channels

A ‘channel’ of the prior art is usually regarded as a communicationspath which is part of an interface and which can be distinguished fromother paths of that interface without regard to its content. However, inthe case of CDMA, separate communications paths are distinguished onlyby their content. The term ‘logical channel’ is used to distinguish theseparate data streams, which are logically equivalent to channels in theconventional sense. All logical channels and sub-channels of the presentinvention are mapped to a common 64 kilo-symbols per second (ksym/s)QPSK stream. Some channels are synchronized to associated pilot codeswhich are generated from, and perform a similar function to the systemglobal pilot code (GPC). The system pilot signals are not, however,considered logical channels.

Several logical communication channels are used over the RFcommunication link between the RCS and SU. Each logical communicationchannel either has a fixed, pre-determined spreading code or adynamically assigned spreading code. For both pre-determined andassigned codes, the code phase is synchronized with the pilot code.Logical communication channels are divided into two groups: the globalchannel (GC) group includes channels which are either transmitted fromthe base station RCS to all remote SUs or from any SU to the RCS of thebase station regardless of the SU's identity. The channels in the GCgroup may contain information of a given type for all users includingthose channels used by SUs to gain system access. Channels in theassigned channels (AC) group are those channels dedicated tocommunication between the RCS and a particular SU.

The global channels (GC) group provides for: 1) broadcast controllogical channels, which provide point-to-multipoint services forbroadcasting messages to all SUs and paging messages to SUs; and 2)access control logical channels which provide point-to-point services onglobal channels for SUs to access the system and obtain assignedchannels. The RCS of the present invention has multiple access controllogical channels, and one broadcast control group. An SU of the presentinvention has at least one access control channel and at least onebroadcast control logical channel.

The global logical channels controlled by the RCS are the fast broadcastchannel (FBCH) which broadcasts fast changing information concerningwhich services and which access channels are currently available, andthe slow broadcast channel (SBCH) which broadcasts slow changing systeminformation and paging messages. The access channel (AXCH) is used bythe SUs to access an RCS and gain access to assigned channels. Each AXCHis paired with a control channel (CTCH). The CTCH is used by the RCS toacknowledge and reply to access attempts by SUs. The long access pilot(LAXPT) is transmitted synchronously with AXCH to provide the RCS with atime and phase reference.

An assigned channel (AC) group contains the logical channels thatcontrol a single telecommunication connection between the RCS and an SU.The functions developed when an AC group is formed include a pair ofpower control logical message channels for each of the uplink anddownlink connections, and depending on the type of connection, one ormore pairs of traffic channels. The bearer control function performs therequired forward error control, bearer rate modification, and encryptionfunctions.

Each SU 111, 112, 115, 117 and 118 has at least one AC group formed whena telecommunication connection exists, and each RCS 104, 105 and 110 hasmultiple AC groups formed, one for each connection in progress. An ACgroup of logical channels is created for a connection upon successfulestablishment of the connection. The AC group includes encryption, FECcoding and multiplexing on transmission, and FEC decoding, decryptionand demultiplexing on reception.

Each AC group provides a set of connection oriented point-to-pointservices and operates in both directions between a specific RCS, forexample, RCS 104 and a specific SU, for example, SU 111. An AC groupformed for a connection can control more than one bearer over the RFcommunication channel associated with a single connection. Multiplebearers are used to carry distributed data such as, but not limited to,ISDN. An AC group can provide for the duplication of traffic channels tofacilitate switch over to 64 kb/s PCM for high speed facsimile and modemservices for the bearer rate modification function.

The assigned logical channels formed upon a successful call connectionand included in the AC group are a dedicated signaling channel [orderwire (OW)], an APC channel, and one or more traffic channels (TRCH)which are bearers of 8, 16, 32, or 64 kb/s depending on the servicesupported. For voice traffic, moderate rate coded speech, ADPCM or PCMcan be supported on the traffic channels. For ISDN service types, two 64kb/s TRCHs form the B channels and a 16 kb/s TRCH forms the D channel.Alternatively, the APC subchannel may either be separately modulated onits own CDMA channel, or may be time division multiplexed with a trafficchannel or OW channel.

Each SU 111, 112, 115, 117 and 118 of the present invention supports upto three simultaneous traffic channels. The mapping of the three logicalchannels for TRCHs to the user data is shown below in Table 1: TABLE 1Mapping of service types to the three available TRCH channels ServiceTRCH(0) TRCH(1) TRCH(2) 16 kb/s POTS TRCH/16 not used not used 32 + 64kb/s POTS TRCH/32 TRCH/64 not used (during BCM) 32 kb/s POTS TRCH/32 notused not used 64 kb/s POTS not used TRCH/64 not used ISDN D not used notused TRCH/16 ISDN B + D TRCH/64 not used TRCH/16 ISDN 2B + D TRCH/64TRCH/64 TRCH/16 Digital LL @ 64 kb/s TRCH/64 not used not used DigitalLL @ 2 × 64 kb/s TRCH/64 TRCH/64 not used Analog LL @ 64 kb/s TRCH/64not used not used

The APC data rate is sent at 64 kb/s. The APC logical channel is not FECcoded to avoid delay and is transmitted at a relatively low power levelto minimize capacity used for APC. Alternatively, the APC and OW may beseparately modulated using complex spreading code sequences or they maybe time division multilplexed.

The OW logical channel is FEC coded with a rate ½ convolutional code.This logical channel is transmitted in bursts when signaling data ispresent to reduce interference. After an idle period, the OW signalbegins with at least 35 symbols prior to the start of the data frame.For silent maintenance call data, the OW is transmitted continuouslybetween frames of data. Table 2 summarizes the logical channels used inthe exemplary embodiment: TABLE 2 Logical Channels and sub-channels ofthe B-CDMA Air Interface Direction (forward Channel Brief or Bit Maxname Abbr. Description reverse) rate BER Power level Pilot GlobalChannels Fast FBCH Broadcasts F 16 1e−4 Fixed GLPT Broadcastfast-changing kb/s Channel system information Slow SBCH Broadcasts F 161e−7 Fixed GLPT Broadcast paging kb/s Channel messages to FSUs andslow-changing system information Access AXCH(i) For initial R 32 1e−7Controlled LAXPT(i) Channels access kb/s by APC attempts by FSUs ControlCTCH(i) For granting F 32 1e−7 Fixed GLPT Channels access kb/s AssignedChannels 16 kb/s TRCH/ General POTS F/R 16 1e−4 Controlled F-GLPT POTS16 use kb/s by APC R-ASPT 32 kb/s TRCH/ General F/R 32 1e-4 Controlledby APC F-GLPT POTS 32 POTS use kb/s R-ASPT 64 kb/s TRCH/ POTS use forF/R 64 1e−4 Controlled by APC F-GLPT POTS 64 in-band kb/s R-ASPTmodems/fax D TRCH/ ISDN D F/R 16 1e−7 Controlled by APC F-GLPT channel16 channel kb/s R-ASPT Order OW assigned F/R 32 1e−7 Controlled by APCF-GLPT wire signaling kb/s R-ASPT channel channel APC APC carries APCF/R 64 2e−1 Controlled by APC F-GLPT channel commands kb/s R-ASPT

III. The Spreading Codes

The CDMA code generators used to encode the logical channels of thepresent invention employ linear shift registers (LSRs) with feedbacklogic which is a method well known in the art. The code generators ofthe present embodiment of the invention generate 64 synchronous uniquesequences. Each RF communication channel uses a pair of these sequencesfor complex spreading (in-phase and quadrature) of the logical channels,so the generator gives 32 complex spreading sequences. The sequences aregenerated by a single seed which is initially loaded into a shiftregister circuit.

IV. The Generation of Spreading Code Sequences and Seed Selection

The spreading code period of the present invention is defined as aninteger multiple of the symbol duration, and the beginning of the codeperiod is also the beginning of the symbol. The relation betweenbandwidths and the symbol lengths chosen for the exemplary embodiment ofthe present invention is: BW (MHZ) L (chips/symbol) 7 91 10 130 10.5 13314 182 15 195

The spreading code length is also a multiple of 64 and of 96 for ISDNframe support. The spreading code is a sequence of symbols, called chipsor chip values. The general methods of generating pseudorandom sequencesusing Galois Field mathematics is known to those skilled in the art.First, the length of the LFSR to generate a code sequence is chosen, andthe initial value of the register is called a “seed”. Second, theconstraint is imposed that no code sequence generated by a code seed maybe a cyclic shift of another code sequence generated by the same codeseed. Finally, no code sequence generated from one seed may be a cyclicshift of a code sequence generated by another seed. It has beendetermined that the spreading code length of chip values of the presentinvention is:128×233,415=29,877,120  Equation (1)The spreading codes are generated by combining a linear sequence ofperiod 233415 and a nonlinear sequence of period 128.

The FBCH channel of the exemplary embodiment is an exception because itis not coded with the 128 length sequence, so the FBCH channel spreadingcode has period 233415.

The nonlinear sequence of length 128 is implemented as a fixed sequenceloaded into a shift register with a feed-back connection. The fixedsequence can be generated by an m-sequence of length 127 padded with anextra logic 0, 1, or random value as is well known in the art.

The linear sequence of length L=233415 is generated using an LFSRcircuit with 36 stages. The feedback connections correspond to anirreducible polynomial h(n) of degree 36. The polynomial h(x) chosen forthe exemplary embodiment of the present invention ish(x)=x ³⁶ +x ³⁵ +x ³⁰ +x ²⁸ +x ²⁶ +x ²⁵ +x ²² +x ²⁰ +x ¹⁹ +x ¹⁷ +x ¹⁶ +x¹⁵ +x ¹⁴ +x ¹² +x ¹¹ +x ⁹ +x ⁸ +x ⁴ +x ³ +x ²+1or, in binary notationh(x)=(1100001010110010110111101101100011101)  Equation (2)

A group of “seed” values for a LFSR representing the polynomial h(x) ofEquation (2) which generates code sequences that are nearly orthogonalwith each other is determined. The first requirement of the seed valuesis that the seed values do not generate two code sequences which aresimply cyclic shifts of each other.

The seeds are represented as elements of GF(2³⁶) which is the field ofresidue classes modulo h(x). This field has a primitive element δ=x²+x+1or, in binary notationδ=(000000000000000000000000000000000111)  Equation (3)

Every element of GF(2³⁶) can also be written as a power of δ reducedmodulo h(x). Consequently, the seeds are represented as powers of δ, theprimitive element.

The solution for the order of an element does not require a search ofall values; the order of an element divides the order of the field(GF(2³⁶)). When δ is any element of GF(2³⁶) withχ^(e)≡1  Equation (4)for some e, then e|2³⁶−1. Therefore, the order of any element in GF(2³⁶)divides 2³⁶−1. Using these constraints, it has been determined that anumerical search generates a group of seed values, n, which are powersof δ, the primitive element of h(x).

The present invention includes a method to increase the number ofavailable seeds for use in a CDMA communication system by recognizingthat certain cyclic shifts of the previously determined code sequencesmay be used simultaneously. The round trip delay for the cell sizes andbandwidths of the present invention are less than 3000 chips. In oneembodiment of the present invention, sufficiently separated cyclicshifts of a sequence can be used within the same cell without causingambiguity for a receiver attempting to determine the code sequence. Thismethod enlarges the set of sequences available for use.

By implementing the tests previously described, a total of 3879 primaryseeds were determined through numerical computation. These seeds aregiven mathematically as:δ^(n)moduloh(x)  Equation (5)where 3879 values of n, with δ=(00, . . . 00111) as in Equation (3), isa series incrementing by 1, starting at 1 and continuing to 1101,resuming at 2204 and continuing to 3305, resuming at 4408 and continuingto 5509, and resuming at 6612 and ending at 7184.

When all primary seeds are known, all secondary seeds of the presentinvention are derived from the primary seeds by shifting them multiplesof 4095 chips modulo h(x). Once a family of seed values is determined,these values are stored in memory and assigned to logical channels asnecessary. Once assigned, the initial seed value is simply loaded intoLFSR to produce the required spreading code associated with the seedvalue.

V. Rapid Acquisition Feature of Long and Short Codes.

Rapid acquisition of the correct code phase by a spread-spectrumreceiver is improved by designing spreading codes which are faster todetect. The present embodiment of the invention includes a new method ofgenerating spreading codes that have rapid acquisition properties byusing one or more of the following methods. First, a long code may beconstructed from two or more short codes. The new implementation usesmany spreading codes, one or more of which are rapid acquisitionsequences of length L that have average acquisition phase searchesr=log2 L. Sequences with such properties are well known to thosepracticed in the art. The average number of acquisition test phases ofthe resulting long sequence is a multiple of r=log2 L rather than halfof the number of phases of the long sequence.

Second, a method of transmitting complex valued spreading code sequences(in-phase (I) and quadrature (Q) sequences) in a pilot spreading codesignal may be used rather than transmitting real valued sequences. Twoor more separate code sequences may be transmitted over the complexchannels. If the sequences have different phases, an acquisition may bedone by acquisition circuits in parallel over the different spreadingcodes when the relative phase shift between the two or more codechannels is known. For example, for two sequences, one can be sent on anin-phase (I) channel and one on the quadrature (Q) channel. To searchthe code sequences, the acquisition detection means searches the twochannels, but begins the Q channel with an offset equal to one-half ofthe spreading code sequence length. With code secquence length of N, theacquisition means starts the search at N/2 on the Q channel. The averagenumber of tests to find acquisition is N/2 for a single code search, butsearching the I and phase delayed Q channel in parallel reduces theaverage number of test to N/4. The codes sent on each channel could bethe same code, the same code with one channel's code phase delayed ordifferent code sequences.

VI. Epoch and Sub-Epoch Structures

The long complex spreading codes used for the exemplary system of thepresent invention have a number of chips after which the code repeats.The repetition period of the spreading sequence is called an epoch. Tomap the logical channels to CDMA spreading codes, the present inventionuses an epoch and sub-epoch structure. The code period for the CDMAspreading code to modulate logical channels is 29877120 chips/codeperiod, which is the same number of chips for all bandwidths. The codeperiod is the epoch of the present invention, and Table 3 below definesthe epoch duration for the supported chip rates. In addition, twosub-epochs are defined over the spreading code epoch and are 233415chips and 128 chips long.

The 233415 chip sub-epoch is referred to as a long sub-epoch, and isused for synchronizing events on the RF communication interface such asencryption key switching and changing from global to assigned codes. The128 chip short epoch is defined for use as an additional timingreference. The highest symbol rate used with a single CDMA code is 64ksym/s. There are always an integer number of chips in a symbol durationfor the supported symbol rates 64, 32, 16, and 8 ksym/s. TABLE 3Bandwidths, Chip Rates, and Epochs number of 128 chip 233415 chip Band-Chip Rate, chips in a 64 sub-epoch sub-epoch Epoch width Complexkbit/sec duration* duration* duration (MHz) (Mchip/sec) symbol (μs) (ms)(sec) 7 5.824 91 21.978 40.078 5.130 10 8.320 130 15.385 28.055 3.59110.5 8.512 133 15.038 27.422 3.510 14 11.648 182 10.989 20.039 2.565 1512.480 195 10.256 18.703 2.394*numbers in these columns are rounded to 5 digits.

VII. Mapping of the Logical Channels to Epochs and Sub-Epochs

The complex spreading codes are designed such that the beginning of thesequence epoch coincides with the beginning of a symbol for all of thebandwidths supported. The present invention supports bandwidths of 7,10, 10.5, 14, and 15 MHz. Assuming nominal 20% roll-off, thesebandwidths correspond to the following chip rates in Table 4. TABLE 4Supported Bandwidths and Chip Rates for CDMA. R_(c) (Complex ExcessFactorization of BW (MHz) Mchips/sec) BW, % L: (R_(c)/L) = 64k L 7 5.82420.19 91 7 × 13 10 8.320 20.19 130 2 × 5 × 13 10.5 8.512 23.36 133 7 ×19 14 11.648 20.19 182 2 × 7 × 13 15 12.480 20.19 195 3 × 5 × 13The number of chips in an epoch is:N=29877120=2⁷×3³×5×7×13×19  Equation (6)

If interleaving is used, the beginning of an interleaver periodcoincides with the beginning of the sequence epoch. The spreadingsequences generated using the method of the present invention cansupport interleaver periods that are multiples of 1.5 ms for variousbandwidths.

Cyclic sequences of the prior art are generated using LFSR circuits.However, this method does not generate sequences of even length. Oneembodiment of the spreading code generator using the code seedsgenerated previously is shown in FIG. 2 a, FIG. 2 b, and FIG. 2 c. Thepresent invention uses a 36 stage LFSR 201 to generate a sequence ofperiod N′=233415=3³×5×7×13×19, which is C₀ in FIG. 2 a. In FIGS. 2 a, 2b, and 2 c, the symbol ⊕ represents a binary addition (EXCLUSIVE-OR). Aspreading code generator designed as above generates the in-phase andquadrature parts of a set of complex sequences. The tap connections andinitial state of the 36 stage LFSR determine the sequence generated bythis circuit. The tap coefficients of the 36 stage LFSR are determinedsuch that the resulting sequences have the period 233415. Note that thetap connections shown in FIG. 2 a correspond to the polynomial given inEquation (2). Each resulting sequence is then overlaid by binaryaddition with the 128 length sequence C* to obtain the epoch period29877120.

FIG. 2 b shows a feed forward (FF) circuit 202 which is used in the codegenerator. The signal X[n−1] is output of the chip delay 211, and theinput of the chip delay 211 is X[n]. The code chip C[n] is formed by thelogical adder 212 from the input X[n] and X[n−1]. FIG. 2 c shows thecomplete spreading code generator. From the LFSR 201, output signals gothrough a chain of up to 63 single stage FFs 203 cascaded as shown. Theoutput of each FF is overlaid with the short, even code sequence C*period 128=2⁷ which is stored in code memory 222 and which exhibitsspectral characteristics of a pseudorandom sequence to obtain the epochN=29877120. This sequence of 128 is determined by using an m-sequence(PN sequence) of length 127=2⁷−1 and adding a bit-value, such as logic0, to the sequence to increase the length to 128 chips. The even codesequence C* is input to the even code shift register 221, which is acyclic register, that continually outputs the sequence. The shortsequence is then combined with the long sequence using an EXCLUSIVE-ORoperation 213, 214, 220.

As shown in FIG. 2 c, up to 63 spreading code sequences C₀ through C₆₃are generated by tapping the output signals of FFs 203 and logicallyadding the short sequence C* in binary adders 213, 214, and 220, forexample. One skilled in the art would realize that the implementation ofFF 203 will create a cumulative delay effect for the code sequencesproduced at each FF stage in the chain. This delay is due to the nonzeroelectrical delay in the electronic components of the implementation. Thetiming problems associated with the delay can be mitigated by insertingadditional delay elements into the FF chain in one version of theembodiment of the invention. The FF chain of FIG. 2 c with additionaldelay elements is shown in FIG. 2 d.

The code-generators in the exemplary embodiment of the present inventionare configured to generate either global codes or assigned codes. Globalcodes are CDMA codes that can be received or transmitted by all users ofthe system. Assigned codes are CDMA codes that are allocated for aparticular connection. When a set of sequences are generated from thesame generator as described, only the seed of the 36 stage LFSR isspecified to generate a family of sequences. Sequences for all of theglobal codes are generated using the same LFSR circuit. Therefore, oncean SU has synchronized to the global pilot signal from an RCS and knowsthe seed for the LFSR circuit for the global channel codes, it cangenerate not only the pilot sequence but also all other global codesused by the RCS.

The signal that is upconverted to RF is generated as follows. The outputsignals of the above shift register circuits are converted to anantipodal sequence (0 maps into +1, 1 maps into −1). The logicalchannels are initially converted to QPSK signals, which are mapped asconstellation points as is well known in the art. The in-phase andquadrature channels of each QPSK signal form the real and imaginaryparts of the complex data value. Similarly, two spreading codes are usedto form complex spreading chip values. The complex data are spread bybeing multiplied by the complex spreading code. Similarly, the receivedcomplex data is correlated with the conjugate of the complex spreadingcode to recover despread data.

VIII. Short Codes

Short codes are used for the initial ramp-up process when a SU accessesan RCS. The period of the short codes is equal to the symbol durationand the start of each period is aligned with a symbol boundary. Both SUand RCS derive the real and imaginary parts of the short codes from thelast eight feed-forward sections of the sequence generator producing theglobal codes for that cell.

The short codes that are in use in the exemplary embodiment of theinvention are updated every 3 ms. Other update times that are consistentwith the symbol rate may be used. Therefore, a change-over occurs every3 ms starting from the epoch boundary. At a change-over, the next symbollength portion of the corresponding feed-forward output becomes theshort code. When the SU needs to use a particular short code, it waitsuntil the first 3 ms boundary of the next epoch and stores the nextsymbol length portion output from the corresponding FF section. Thisshall be used as the short code until the next change-over, which occurs3 ms later.

The signals represented by these short codes are known as short accesschannel pilots (SAXPTs).

IX. Mapping of Logical Channels to Spreading Codes

The exact relationship between the spreading code sequences and the CDMAlogical channels and pilot signals is documented in Table 5a and Table5b. Those signal names ending in ‘-CH’ correspond to logical channels.Those signal names ending in ‘-PT’ correspond to pilot signals, whichare described in detail below. TABLE 5a Spreading code sequences andglobal CDMA codes Sequence Quadrature Logical Channel or Pilot SignalDirection C₀ I FBCH Forward (F) C₁ Q FBCH F C₂⊕C* I GLPT F C₃⊕C* Q GLPTF C₄⊕C* I SBCH F C₅⊕C* Q SBCH F C₆⊕C* I CTCH (0) F C₇⊕C* Q CTCH (0) FC₈⊕C* I APCH (1) F C₉⊕C* Q APCH (1) F C₁₀⊕C* I CTCH (1) F C₁₁⊕C* Q CTCH(1) F C₁₂⊕C* I APCH (1) F C₁₃⊕C* Q APCH (1) F C₁₄⊕C* I CTCH (2) F C₁₅⊕C*Q CTCH (2) F C₁₆⊕C* I APCH (2) F C₁₇⊕C* Q APCH (2) F C₁₈⊕C* I CTCH (3) FC₁₉⊕C* Q CTCH (3) F C₂₀⊕C* I APCH (3) F C₂₁⊕C* Q APCH (3) F C₂₂⊕C* Ireserved — C₂₃⊕C* Q reserved — . . . . . . . . . . . . C₄₀⊕C* I reserved— C₄₁⊕C* Q reserved — C₄₂⊕C* I AXCH(3) Reverse (R) C₄₃⊕C* Q AXCH(3) RC₄₄⊕C* I LAXPT(3) R SAXPT(3) seed C₄₅⊕C* Q LAXPT(3) seed R SAXPT(3) seedC₄₆⊕C* I AXCH(2) R C₄₇⊕C* Q AXCH(2) R C₄₈⊕C* I LAXPT(2) R SAXPT(2) seedC₄₉⊕C* Q LAXPT(2) seed R SAXPT(2) seed C₅₀⊕C* I AXCH(1) R C₅₁⊕C* QAXCH(1) R C₅₂⊕C* I LAXPT(1) R SAXPT(1) seed C₅₃⊕C* Q LAXPT(1) seed RSAXPT(1) seed C₅₄⊕C* I AXCH(0) R C₅₅⊕C* Q AXCH(0) R C₅₆⊕C* I LAXPT(0) RSAXPT(0) seed C₅₇⊕C* Q LAXPT(0) seed R SAXPT(0) seed C₅₈⊕C* I IDLE —C₅₉⊕C* Q IDLE — C₆₀⊕C* I AUX R C₆₁⊕C* Q AUX R C₆₂⊕C* I reserved — C₆₃⊕C*Q reserved —

TABLE 5b Spreading code sequences and assigned CDMA codes. LogicalChannel Sequence Quadrature or Pilot Signal Direction C₀⊕C* I ASPTReverse (R) C₁⊕C* Q ASPT R C₂⊕C* I APCH R C₃⊕C* Q APCH R C₄⊕C* I OWCH RC₅⊕C* Q OWCH R C₆⊕C* I TRCH(0) R C₇⊕C* Q TRCH(0) R C₈⊕C* I TRCH(1) RC₉⊕C* Q TRCH(1) R C₁₀⊕C* I TRCH(2) R C₁₁⊕C* Q TRCH(2) R C₁₂⊕C* I TRCH(3)R C₁₃⊕C* Q TRCH(3) R C₁₄⊕C* I reserved — C₁₅⊕C* Q reserved — . . . . . .. . . . . . C₄₄⊕C* I reserved — C₄₅⊕C* Q reserved — C₄₆⊕C* I TRCH(3)Forward (F) C₄₇⊕C* Q TRCH(3) F C₄₈⊕C* I TRCH(2) F C₄₉⊕C* Q TRCH(2) FC₅₀⊕C* I TRCH(1) F C₅₁⊕C* Q TRCH(1) F C₅₂⊕C* I TRCH(0) F C₅₃⊕C* QTRCH(0) F C₅₄⊕C* I OWCH F C₅₅⊕C* Q OWCH F C₅₆⊕C* I APCH F C₅₇⊕C* Q APCHF C₅₈⊕C* I IDLE — C₅₉⊕C* Q IDLE — C₆₀⊕C* I reserved — C₆₁⊕C* Q reserved— C₆₂⊕C* I reserved — C₆₃⊕C* Q reserved —

For global codes, the seed values for the 36 bit shift register arechosen to avoid using the same code, or any cyclic shift of the samecode, within the same geographical area to prevent ambiguity or harmfulinterference. No assigned code is equal to, or a cyclic shift of, aglobal code.

X. Pilot Signals

The pilot signals are used for synchronization, carrier phase recoveryand for estimating the impulse response of the radio channel. The RCS104 transmits a forward link pilot carrier reference as a complex pilotcode sequence to provide time and phase reference for all SUs 111, 112,115, 117 and 118 in its service area. The power level of the globalpilot (GLPT) signal is set to provide adequate coverage over the wholeRCS service area, which area depends on the cell size. With only onepilot signal in the forward link, the reduction in system capacity dueto the pilot energy is negligible.

The SUs 111, 112, 115, 117 and 118 each transmit a pilot carrierreference as a quadrature modulated (complex-valued) pilot spreadingcode sequence to provide a time and phase reference to the RCS for thereverse link. The pilot signal transmitted by the SU of one embodimentof the invention is 6 dB lower than the power of the 32 kb/s POTStraffic channel. The reverse pilot channel is subject to APC. Thereverse link pilot associated with a particular connection is called theassigned pilot (ASPT). In addition, there are pilot signals associatedwith access channels. These are called the long access channel pilots(LAXPTs). Short access channel pilots (SAXPTs) are also associated withthe access channels and used for spreading code acquisition and initialpower ramp-up. All pilot signals are formed from complex codes, asdefined below:

-   GLPT (forward)={C₂⊕C*)+j.(C₃⊕C*)}.{(1)+j.(0)}{Complex    Code}.{Carrier}

The complex pilot signals are de-spread by multiplication with conjugatespreading codes: {(C₂⊕C*)−j.(C₃⊕C*)}. By contrast, traffic channels areof the form:

-   TRCH_(n)(forward/reverse)={(C_(k)⊕C*)+j.(C₁⊕C*)}.{(±1)+j(±1)}{Complex    Codes}.{Data Symbol}    which thus form a constellation set at $\frac{\pi}{4}$    radians with respect to the pilot signal constellations. The GLPT    constellation is shown in FIG. 3 a, and the TRCH_(n) traffic channel    constellation is shown in FIG. 3 b.

XI. Logical Channel Assignment of the FBCH, SBCH, and Traffic Channels

The FBCH is a global forward link channel used to broadcast dynamicinformation about the availability of services and AXCHs. Messages aresent continuously over this channel, and each message lastsapproximately 1 ms. The FBCH message is 16 bits long, repeatedcontinuously, and is epoch aligned. The FBCH is formatted as defined inTable 6. TABLE 6 FBCH format Bit Definition  0 Traffic Light 0  1Traffic Light 1  2 Traffic Light 2  3 Traffic Light 3 4-7 serviceindicator bits  8 Traffic Light 0  9 Traffic Light 1 10 Traffic Light 211 Traffic Light 3 12-15 service indicator bits

For the FBCH, bit 0 is transmitted first. As used in Table 6, a trafficlight corresponds to an access channel (AXCH) and indicates whether theparticular access channel is currently in use (a red) or not in use (agreen). A logic ‘1’ indicates that the traffic light is green, and alogic ‘0’ indicates the traffic light is red. The values of the trafficlight bits may change from octet to octet and each 16 bit messagecontains distinct service indicator bits which describe the types ofservices that are available for the AXCHs.

One embodiment of the present invention uses service indicator bits asfollows to indicate the availability of services or AXCHs. The serviceindicator bits {4, 5, 6, 7, 12, 13, 14, 15} taken together may be anunsigned binary number, with bit 4 as the MSB and bit 15 as the LSB.Each service type increment has an associated nominal measure of thecapacity required, and the FBCH continuously broadcasts the availablecapacity. This is scaled to have a maximum value equivalent to thelargest single service increment possible. When an SU requires a newservice or an increase in the number of bearers it compares the capacityrequired to that indicated by the FBCH and then considers itself blockedif the capacity is not available. The FBCH and the traffic channels arealigned to the epoch.

Slow broadcast information frames contain system or other generalinformation that is available to all SUs and paging information framescontain information about call requests for particular SUs. Slowbroadcast information frames and paging information frames aremultiplexed together on a single logical channel which forms the slowbroadcast channel (SBCH). As previously defined, the code epoch is asequence of 29,877,120 chips having an epoch duration which is afunction of the chip rate defined in Table 7 below. In order tofacilitate power saving, the channel is divided into N “Sleep” cycles,and each cycle is subdivided into M slots, which are 19 ms long, exceptfor 10.5 MHz bandwidth which has slots of 18 ms. TABLE 7 SBCH ChannelFormat Outline Spreading Epoch Cycles/ Cycle Slots/ Slot Bandwidth CodeRate Length Epoch Length Cycle Length (MHz) (MHz) (ins) N (ms) M (ms)7.0 5.824 5130 5 1026 54 19 10.0 8.320 3591 3 1197 63 19 10.5 8.512 35103 1170 65 18 14.0 11.648 2565 3 855 45 19 15.0 12.480 2394 2 1197 63 19

Sleep cycle slot #1 is always used for slow broadcast information. Slots#2 to #M−1 are used for paging groups unless extended slow broadcastinformation is inserted. The pattern of cycles and slots in oneembodiment of the present invention run continuously at 16 kb/s.

Within each sleep cycle the SU powers-up the receiver and re-acquiresthe pilot code. It then achieves carrier lock to a sufficient precisionfor satisfactory demodulation and Viterbi decoding. The settling time toachieve carrier lock may be up to 3 slots in duration. For example, anSU assigned to Slot #7 powers up the receiver at the start of slot #4.Having monitored its slot the SU will have either recognized its pagingaddress and initiated an access request, or failed to recognize itspaging address in which case it reverts to the sleep mode. Table 8 showsduty cycles for the different bandwidths, assuming a wake-up duration of3 slots. TABLE 8 Sleep-Cycle Power Saving Bandwidth (MHz) Slots/CycleDuty Cycle 7.0 54 7.4% 10.0 63 6.3% 10.5 65 6.2% 14.0 45 8.9% 15.0 636.3%

XII. Spreading Code Tracking and AMF Detection in Multipath Channels

Three CDMA spreading code tracking methods in multipath fadingenvironments are described which track the code phase of a receivedmultipath spread-spectrum signal. The first is the prior art trackingcircuit which simply tracks the spreading code phase with the highestdetector output signal value, the second is a tracking circuit thattracks the median value of the code phase of the group of multipathsignals, and the third is the centroid tracking circuit which tracks thecode-phase of an optimized, least mean squared weighted average of themultipath signal components. The following describes the algorithms bywhich the spreading code phase of the received CDMA signal is tracked.

A tracking circuit has operating characteristics that reveal therelationship between the time error and the control voltage that drivesa voltage controlled oscillator (VCO) of a spreading code phase trackingcircuit. When there is a positive timing error, the tracking circuitgenerates a negative control voltage to offset the timing error. Whenthere is a negative timing error, the tracking circuit generates apositive control voltage to offset the timing error. When the trackingcircuit generates a zero value, this value corresponds to the perfecttime alignment called the ‘lock point’.

FIG. 3 c shows the basic tracking circuit. Received signal r(t) isapplied to matched filter 301, which correlates r(t) with a localcode-sequence c(t) generated by code generator 303. The output signal ofthe matched filter x(t) is sampled at the sampler 302 to produce samplesx[nT] and x[nT+T/2]. The samples x[nT] and x[nT+T/2] are used by atracking circuit 304 to determine if the phase of the spreading codec(t) of the code generator 303 is correct. The tracking circuit 304produces an error signal e(t) as an input to the code generator 303. Thecode generator 303 uses this signal e(t) as an input signal to adjustthe code-phase it generates.

In a CDMA system, the signal transmitted by the reference user iswritten in the low-pass representation as: $\begin{matrix}{{s(t)} = {\sum\limits_{k = {- \infty}}^{\infty}{C_{k}{P_{Tc}\left( {t - {k\quad T_{c}}} \right)}}}} & {{Equation}\quad(7)}\end{matrix}$where C_(k) represents the spreading code coefficients, P_(Tc)(t)represents the spreading code chip waveform and T_(c) is the chipduration. Assuming that the reference user is not transmitting data sothat only the spreading code modulates the carrier. Referring to FIG. 3c, the received signal is: $\begin{matrix}{{r(t)} = {\sum\limits_{i = 1}^{M}{a_{i}{s\left( {t - \tau_{i}} \right)}}}} & {{Equation}\quad(8)}\end{matrix}$Here, a_(i) is due to fading effect of the multipath channel on the i-thpath and τ_(i) is the random time delay associated with the same path.The receiver passes the received signal through a matched filter, whichis implemented as a correlation receiver and is described below. Thisoperation is done in two steps: first the signal is passed through achip matched filter and sampled to recover the spreading code chipvalues; then this chip sequence is correlated with the locally generatedcode sequence.

FIG. 3 c shows the chip matched filter 301, matched to the chip waveformP_(Tc)(t), and the sampler 302. Ideally, the signal x(t) at the outputterminal of the chip matched filter 301 is: $\begin{matrix}{{x(t)} = {\sum\limits_{i = k}^{M}{\sum\limits_{k = {- \infty}}^{\infty}{a_{i}c_{k}{g\left( {t - \tau_{i} - {k\quad T_{c}}} \right)}}}}} & {{Equation}\quad(9)}\end{matrix}$where:g(t)=P _(Tc)(t)*h _(R)(t)  Equation (10)M is the number of multipath components. Here, h_(R)(t) is the impulseresponse of the chip matched filter 301 and ‘*’ denotes convolution. Theorder of the summations can be rewritten as: $\begin{matrix}{{x(t)} = {\sum\limits_{k = {- \infty}}^{\infty}{c_{k}\quad{f\left( {t - {k\quad T_{c}}} \right)}}}} & {{Equation}\quad(11)} \\{{where}\text{:}} & \quad \\{{f(t)} = {\sum\limits_{i = 1}^{M}{a_{i}{g\left( {t - \tau_{i}} \right)}}}} & {{Equation}\quad(12)}\end{matrix}$In the multipath channel described above, the sampler 302 samples theoutput signal of the chip matched filter 301 to produce x(nT) at themaximum power level points of g(t). In practice, however, the waveformg(t) is severely distorted because of the effect of the multipath signalreception, and a perfect time alignment of the signals is not available.

When the multipath distortion in the channel is negligible and a perfectestimate of the timing is available, i.e., a₁=1, τ₁=0, and a_(i)=0, i=2,. . . , M, the received signal is r(t)=s(t). Then, with this idealchannel model, the output of the chip matched filter becomes:$\begin{matrix}{{x(t)} = {\sum\limits_{k = {- \infty}}^{\infty}{c_{k}{g\left( {t - {k\quad T_{c}}} \right)}}}} & {{Equation}\quad(13)}\end{matrix}$

When there is multipath fading, however, the received spreading codechip value waveform is distorted, and has a number of local maxima thatcan change from one sampling interval to another depending on thechannel characteristics. For multipath fading channels with quicklychanging channel characteristics, it is not practical to try to locatethe maximum of the waveform f(t) in every chip period interval. Instead,a time reference may be obtained from the characteristics of f(t) thatmay not change as quickly. Three tracking methods are described based ondifferent characteristics of f(t).

XIII. Prior Art Spreading Code Tracking Method:

Prior art tracking methods include a code tracking circuit in which thereceiver attempts to determine the timing of the maximum matched filteroutput value of the chip waveform occurs and samples the signalaccordingly. However, in multipath fading channels, the receiverdespread code waveform can have a number of local maxima, especially ina mobile environment. In the following, f(t) represents the receivedsignal waveform of the spreading code chip convolved with the channelimpulse response. The frequency response characteristic of f(t) and themaximum of this characteristic can change rather quickly making itimpractical to track the maximum of f(t).

Define τ to be the time estimate that the tracking circuit calculatesduring a particular sampling interval. Also, define the following errorfunction as: $\begin{matrix}\begin{matrix}{ɛ = \left\{ {\int\underset{\{{t:{{{\tau - t}}:{- \delta}}}\}}{{f(t)}\quad{\mathbb{d}t}}} \right.} & \quad & {{{\tau - t}} > \delta} \\{ɛ = 0} & \quad & {{{\tau - t}} < \delta}\end{matrix} & {{Equation}\quad(14)}\end{matrix}$The tracking circuits of the prior art calculate a value of the inputsignal that minimizes the error ε. One can write: $\begin{matrix}{{\min\quad ɛ} = {1 - {\max\limits_{\tau}\quad{\int_{\tau - \delta}^{\tau + \delta}{{f(t)}\quad{\mathbb{d}t}}}}}} & {{Equation}\quad(15)}\end{matrix}$

Assuming f(t) has a smooth shape in the values given, the value of τ forwhich f(t) is maximum minimizes the error ε, so the tracking circuittracks the maximum point of f(t).

XIV. Median Weighted Value Tracking Method

The median weighted tracking method of one embodiment of the presentinvention, minimizes the absolute weighted error, defined as:ε=∫_(−∞) ^(∞) |t−τ|f(t)dt  Equation (16)This tracking method calculates the ‘median’ signal value of f(τ) bycollecting information from all paths, where f(τ) is as in Equation(12). In a multipath fading environment, the waveform f(t) can havemultiple local maxima, but only one median. To minimize ε, thederivative of Equation (16) is taken with respect to τ and the result isequated to zero, which provides:∫_(−∞) ^(τ) f(t)dt=∫_(τ) ^(∞) f(t)dt  Equation (17)The value of τ that satisfies Equation (17) is called the ‘median’off(t). Therefore, the median tracking method of the present embodimenttracks the median of f(t).

FIG. 4 shows an implementation of the tracking circuit based onminimizing the absolute weighted error defined above. The signal x(t)and its one-half chip offset version x(t+T/2) are sampled by the A/Dconverter 401 at a rate 1/T. The following Equation determines theoperating characteristic of the circuit in FIG. 4: $\begin{matrix}{{ɛ(\tau)} = {{\sum\limits_{n = 1}^{2L}{{f\left( {\tau - {n\quad{T/2}}} \right)}}} - {{f\left( {\tau + {n\quad{T/2}}} \right)}}}} & {{Equation}\quad(18)}\end{matrix}$

Tracking the median of a group of multipath signals keeps the receivedenergy of the multipath signal components substantially equal on theearly and late sides of the median point of the correct locallygenerated spreading code phase c_(n). The tracking circuit consists ofan A/D converter 401 which samples an input signal x(t) to form thehalf-chip offset samples. The half-chip offset samples x(nT+τ) and oddsamples called a late set of samples x(nT+(T/2)+τ). The firstcorrelation bank adaptive matched filter 402 multiplies each earlysample by the spreading code phases c(n+1), c(n+2), . . . , c(n+L),where L is small compared to the code length and is approximately equalto the number of chips of delay between the earliest and latestmultipath signal. The output of each correlator is applied to arespective first sum-and-dump bank 404. The magnitudes of the outputvalues of the L sum-and-dumps are calculated in the calculator 406 andthen summed in summer 408 to give an output value proportional to thesignal energy in the early multipath signals. Similarly, a secondcorrelation bank adaptive matched filter 403 operates on the latesamples, using code phases c(n−1), c(n−2), . . . , c(n−L), and eachoutput signal is applied to a respective sum-and-dump circuit in anintegrator 405. The magnitudes of the L sum-and-dump output signals arecalculated in calculator 407 and then summed in summer 409 to give avalue for the late multipath signal energy. Finally, the subtractor 410calculates the difference and produces error signal ε(τ) of the earlyand late signal energy values.

The tracking circuit adjusts by means of error signal ε(τ) the locallygenerated code phases c(t) to cause the difference between the early andlate values to tend toward 0.

XV. Centroid Tracking Method

The optimal spreading code tracking circuit of one embodiment of thepresent invention is called the squared weighted tracking (or centroid)circuit. Defining t to denote the time estimate that the trackingcircuit calculates, based on some characteristic of f(t), the centroidtracking circuit minimizes the squared weighted error defined as:ε=∫_(−∞) ^(∞) |t−τ| ² f(t)dt  Equation (19)This function inside the integral has a quadratic form, which has aunique minimum. The value of τ that minimizes ε can be found by takingthe derivative of the above Equation (19) with respect to τ and equatingto zero, which gives:∫_(−∞) ^(∞)(−2t+2τ)f(t)dt=0  Equation (20)Therefore, the value of τ that satisfies Equation (21) is:$\begin{matrix}{{\tau - {\frac{1}{\beta}\quad{\int_{- \infty}^{\infty}{t\quad{f(t)}\quad{\mathbb{d}t}}}}} = 0} & {{Equation}\quad(21)}\end{matrix}$is the timing estimate that the tracking circuit calculates, where β isa constant value.

Based on these observations, a realization of an exemplary trackingcircuit which minimizes the squared weighted error is shown in FIG. 5 a.The following Equation (22) determines the error signal δ(τ) of thecentroid tracking circuit: $\begin{matrix}{{ɛ(\tau)} = {{\sum\limits_{n = 1}^{2L}{n\quad\left\lbrack {{{f\left( {\tau - {n\quad{T/2}}} \right)}} - {{f\left( {\tau + {n\quad{T/2}}} \right)}}} \right\rbrack}} = 0}} & {{Equation}\quad(22)}\end{matrix}$The value that satisfies ε(τ)=0 is the perfect estimate of the timing.

The early and late multipath signal energy on each side of the centroidpoint are equal. The centroid tracking circuit shown in FIG. 5 aconsists of an A/D converter 501 which samples an input signal x(t) toform the half-chip offset samples. The half-chip offset samples arealternately grouped as an early set of samples x(nT+τ) and a late set ofsamples x(nT+(T/2)+τ). The first correlation bank adaptive matchedfilter 502 multiplies each early sample and each late sample by thepositive spreading code phases c(n+1), c(n+2), . . . , c(n+L), where Lis small compared to the code length and approximately equal to thenumber of chips of delay between the earliest and latest multipathsignal. The output signal of each correlator is applied to a respectiveone of L sum-and-dump circuits of the first sum and dump bank 504. Themagnitude value of each sum-and-dump circuit of the sum and dump bank504 is calculated by the respective calculator in the calculator bank506 and applied to a corresponding weighting amplifier of the firstweighting bank 508. The output signal of each weighting amplifierrepresents the weighted signal energy in a multipath component signal.

The weighted early multipath signal energy values are summed in sampleadder 510 to give an output value proportional to the signal energy inthe group of multipath signals corresponding to positive code phaseswhich are the early multipath signals. Similarly, a second correlationbank adaptive matched filter 503 operates on the early and late samples,using the negative spreading code phases c(n−1), c(n−2), . . . , c(n−L);each output signal is provided to a respective sum-and-dump circuit ofdiscrete integrator 505. The magnitude value of the L sum-and-dumpoutput signals are calculated by the respective calculator of calculatorbank 507 and then weighted in weighting bank 509. The weighted latemultipath signal energy values are summed in sample adder 511 to give anenergy value for the group of multipath signals corresponding to thenegative code phases which are the late multipath signals. Finally, theadder 512 calculates the difference of the early and late signal energyvalues to produce error sample value ε(τ).

The tracking circuit of FIG. 5 a produces error signal ε(τ) which isused to adjust the locally generated code phase c(nT) to keep theweighted average energy in the early and late multipath signal groupsequal. The embodiment shown uses weighting values that increase as thedistance from the centroid increases. The signal energy in the earliestand latest multipath signals is probably less than the multipath signalvalues near the centroid. Consequently, the difference calculated by theadder 510 is more sensitive to variations in delay of the earliest andlatest multipath signals.

XVI. Quadratic Detector for Tracking

In this embodiment of the tracking method, the tracking circuit adjuststhe sampling phase to be “optimal” and robust to multipath. Let f(t)represent the received signal waveform as in Equation (12) above. Theparticular method of optimizing starts with a delay locked loop with anerror signal ε(τ) that drives the loop. The function ε(τ) must have onlyone zero at τ=τ₀ where τ₀ is optimal. The optimal form for ε(τ) has thecanonical form: $\begin{matrix}{{ɛ(\tau)} = {\int_{- \infty}^{\infty}{{w\left( {t,\tau} \right)}\quad{{f(t)}}^{2}\quad{\mathbb{d}t}}}} & {{Equation}\quad(23)}\end{matrix}$where w(t,τ) is a weighting function relating f(t) to the error ε(τ),and the relationship indicated by Equation (24) also holds:$\begin{matrix}{{ɛ\left( {\tau + \tau_{0}} \right)} = {\int_{- \infty}^{\infty}{{w\left( {t,{\tau + \tau_{0}}} \right)}\quad{{f(t)}}^{2}\quad{\mathbb{d}t}}}} & {{Equation}\quad(24)}\end{matrix}$

It follows from Equation (24) that w(t,τ) is equivalent to w(t−τ).Considering the slope M of the error signal in the neighborhood of alock point τ₀: $\begin{matrix}{M = {\left. \frac{\mathbb{d}{ɛ(\tau)}}{\mathbb{d}\tau} \right|_{\tau\quad 0} = {- {\int_{- \infty}^{\infty}{{w^{\prime}\left( {t - \tau_{0}} \right)}\quad{g(t)}\quad{\mathbb{d}t}}}}}} & {{Equation}\quad(25)}\end{matrix}$where w′(t, τ) is the derivative of w(t, τ) with respect to τ, and g(t)is the average of |f(t)|².

The error ε(τ) has a deterministic part and a noise part. Let z denotethe noise component in ε(τ), then |z|² is the average noise power in theerror function ε(τ). Consequently, the optimal tracking circuitmaximizes the ratio $\begin{matrix}{F = \frac{M^{2}}{{z}^{2}}} & {{Equation}\quad(26)}\end{matrix}$

The implementation of the quadratic detector is now described. Thediscrete error value e of an error signal ε(τ) is generated byperforming the operatione=y ^(T) By  Equation (27)

where the vector y represents the received signal components yi, i=0, 1,. . . L−1, as shown in FIG. 5 b. The matrix B is an L by L matrix andthe elements are determined by calculating values such that the ratio Fof Equation (26) is maximized. The quadratic detector described abovemay be used to implement the centroid tracking system described abovewith reference to FIG. 5 a. For this implementation, the vector y is theoutput signal of the sum and dump circuits 504: y={f(τ−LT), f(τ−LT+T/2),f(τ−(L−1)T), . . . f(τ), f(τ+T/2), f(τ+T), . . . f(τ+LT)} and the matrixB is set forth in Table 9. TABLE 9 B matrix for quadratic form ofCentroid Tracking System L 0 0 0 0 0 0 0 0 0 0 0 L − 0 0 0 0 0 0 0 0 0 ½0 0 L − 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 0 0 0 0 ½ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 −½ 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 0 0 0 0 0 0 0 0 −L + 1 0 0 0 0 0 0 0 0 0 0 0 −L + ½ 0 0 0 0 0 00 0 0 0 0 −L

XVII. Determining the Minimum Value of L Needed:

The value of L in the previous section determines the minimum number ofcorrelators and sum-and-dump elements. L is chosen as small as possiblewithout compromising the functionality of the tracking circuit.

The multipath characteristic of the channel is such that the receivedchip waveform f(t) is spread over QT_(c) seconds, or the multipathcomponents occupy a time period of Q chips duration. The value of Lchosen is L=Q. Q is found by measuring the particular RF channeltransmission characteristics to determine the earliest and latestmultipath component signal propagation delay. QT_(c) is the differencebetween the earliest and latest multipath component arrival time at areceiver.

XVIII. Adaptive Vector Correlator

An embodiment of the present invention uses an adaptive vectorcorrelator (AVC) to estimate the channel impulse response and to obtaina reference value for coherent combining of received multipath signalcomponents. The described embodiment employs an array of correlators toestimate the complex channel response affecting each multipathcomponent. The receiver compensates for the channel response andcoherently combines the received multipath signal components. Thisapproach is referred to as maximal ratio combining.

Referring to FIG. 6, the input signal x(t) to the system includesinterference noise of other message channels, multipath signals of themessage channels, thermal noise, and multipath signals of the pilotsignal. The signal is provided to AVC 601 which, in the exemplaryembodiment, includes a despreading means 602, channel estimation meansfor estimating the channel response 604, correction means for correctinga signal for effects of the channel response 603 and adder 605. The AVCdespreading means 602 is composed of multiple code correlators, witheach correlator using a different phase of the pilot code c(t) providedby the pilot code generator 608. The output signal of this despreadingmeans corresponds to a noise power level if the local pilot code of thedespreading means is not in phase with the input code signal.Alternatively, it corresponds to a received pilot signal power levelplus noise power level if the phases of the input pilot code and locallygenerated pilot code are the same. The output signals of the correlatorsof the despreading means are corrected for the channel response by thecorrection means 603 and are applied to the adder 605 which collects allmultipath pilot signal power. The channel response estimation means 604receives the combined pilot signal and the output signals of thedespreading means 602, and provides a channel response estimate signal,w(t), to the correction means 603 of the AVC, and the estimate signalw(t) is also available to the adaptive matched filter (AMF) describedbelow. The output signal of the despreading means 602 is also providedto the acquisition decision means 606 which decides, based on aparticular algorithm such as a sequential probability ratio test (SPRT),if the present output levels of the despreading circuits correspond tosynchronization of the locally generated code to the desired input codephase. If the detector finds no synchronization, then the acquisitiondecision means sends a control signal a(t) to the local pilot codegenerator 608 to offset its phase by one or more chip period. Whensynchronization is found, the acquisition decision means informstracking circuit 607, which achieves and maintains a closesynchronization between the received and locally generated spreadingcodes.

An exemplary implementation of the pilot AVC used to despread the pilotspreading code is shown in FIG. 7. The described embodiment assumes thatthe input signal x(τ) has been sampled with sampling period T to formsamples x(nT+τ), and is composed of interference noise of other messagechannels, multipath signals of message channels, thermal noise andmultipath signals of the pilot code. The signal x(nT+τ) is applied to Lcorrelators, where L is the number of code phases over which theuncertainty within the multipath signals exists. Each correlator 701,702, 703 comprises a multiplier 704, 705, 706, which multiples the inputsignal with a particular phase of the pilot spreading code signalc((n+i)T) and sum-and-dump circuits 708, 709, 710. The output signal ofeach multiplier 704, 705, 706 is applied to a respective sum-and dumpcircuit 708, 709, 710 to perform discrete integration. Before summingthe signal energy contained in the outputs of the correlators, the AVCcompensates for the channel response and the carrier phase rotation ofthe different multipath signals. Each output of each sum-and-dump 708,709, 710 is multiplied with a derotation phaser [complex conjugate ofep(nT)] from digital phase lock loop (DPLL) 721 by the respectivemultiplier 714, 715, 716 to account for the phase and frequency offsetof the carrier signal. The pilot rake AMF calculates the weightingfactors wk, k=1, . . . , L, for each multipath signal by passing theoutput of each multiplier 714, 715, 716 through a low pass filter (LPF)711, 712, 713. Each despread multipath signal is multiplied by itscorresponding weighting factor in a respective multiplier 717, 718, 719.The output signals of the multipliers 717, 718, 719 are summed in amaster adder 720, and the output signal p(nT) of the accumulator 720consists of the combined despread multipath pilot signals in noise. Theoutput signal p(nT) is also input to the DPLL 721 to produce the errorsignal ep(nT) for tracking of the carrier phase.

FIGS. 8 a and 8 b show alternate embodiments of the AVC which can beused for detection and multipath signal component combining. The messagesignal AVCs of FIGS. 8 a and 8 b use the weighting factors produced bythe pilot AVC to correct the message data multipath signals. Thespreading code signal, c(nT) is the spreading code spreading sequenceused by a particular message channel and is synchronous with the pilotspreading code signal. The value L is the number of correlators in theAVC circuit.

The circuit of FIG. 8 a calculates the decision variable Z which isgiven by: $\begin{matrix}{Z = {{w_{1}\quad{\sum\limits_{i = 1}^{N}{{x\left( {{i\quad T} + \tau} \right)}\quad{c\left( {i\quad T} \right)}}}} + {w_{2}\quad{\sum\limits_{i = 1}^{N}{{x\left( {{i\quad T} + \tau} \right)}\quad{c\left( {\left( {i + 1} \right)\quad T} \right)}}}} + \ldots + {w_{L}\quad{\sum\limits_{i = 1}^{L}{x\left( {{i\quad T} + \tau} \right)}}} + {c\left( {\left( {i + L} \right)T} \right)}}} & {{Equation}\quad(28)}\end{matrix}$where N is the number of chips in the correlation window. Equivalently,the decision statistic is given by: $\begin{matrix}\begin{matrix}{Z = {{{x\left( {T + \tau} \right)}\quad{\sum\limits_{i = 1}^{L}{w_{1}{c\left( {i\quad T} \right)}}}} +}} \\{{x\left( {{2\quad T} + \tau} \right)}\quad{\sum\limits_{i = 1}^{L}{w_{1}{c\left( {{\left( {i + 1} \right)T} + \cdots +} \right.}}}} \\{{x\left( {{N\quad T} + \tau} \right)}\quad{\sum\limits_{i = 1}^{L}{w_{N}\quad{c\left( {\left( {i + N} \right)T} \right)}}}} \\{= {\sum\limits_{k = 1}^{N}{{x\left( {{k\quad T} - \tau} \right)}\quad{\sum\limits_{i = 1}^{L}{w_{k}\quad{c\left( {\left( {i + k - 1} \right)T} \right)}}}}}}\end{matrix} & {{Equation}\quad(29)}\end{matrix}$The alternative implementation that results from Equation (29) is shownin FIG. 8 b.

Referring to FIG. 8 a, the input signal x(t) is sampled to form x(nT+τ),and is composed of interference noise of other message channels,multipath signals of message channels, thermal noise, and multipathsignals of the pilot code. The signal x(nT+τ) is applied to Lcorrelators, where L is the number of code phases over which theuncertainty within the multipath signals exists. Each correlator 801,802, 803 comprises a multiplier 804, 805, 806, which multiples the inputsignal by a particular phase of the message channel spreading codesignal, and a respective sum-and-dump circuit 808, 809, 810. The outputsignal of each multiplier 804, 805, 806 is applied to a respectivesum-and dump circuit 808, 809, 810 which performs discrete integration.Before summing the signal energy contained in the output signals of thecorrelators, the AVC compensates for the different multipath signals.Each despread multipath signal and its corresponding weighting factor,which is obtained from the corresponding multipath weighting factor ofthe pilot AVC, are multiplied in a respective multiplier 817, 818, 819.The output signals of multipliers 817, 818, 819 are summed in a masteradder 820, and the output signal z(nT) of the accumulator 820 consistsof sampled levels of a despread message signal in noise.

The alternative embodiment of the invention includes a newimplementation of the AVC despreading circuit for the message channelswhich performs the sum-and-dump for each multipath signal componentsimultaneously. The advantage of this circuit is that only one sum-anddump circuit and one adder is necessary. Referring to FIG. 8 b, themessage code sequence generator 830 provides a message code sequence toshift register 831 of length L. The output signal of each register 832,833, 834, 835 of the shift register 831 corresponds to the message codesequence shifted in phase by one chip. The output value of each register832, 833, 834, 835 is multiplied in multipliers 836, 837, 838, 839 withthe corresponding weighting factor w_(k), k=1, . . . , L obtained fromthe pilot AVC. The output signals of the L multipliers 836, 837, 838,839 are summed by the adding circuit 840. The adding circuit outputsignal and the receiver input signal x(nT+τ) are then multiplied in themultiplier 841 and integrated by the sum-and-dump circuit 842 to producemessage signal z(nT).

A third embodiment of the adaptive vector correlator is shown in FIG. 8c. The embodiment shown uses the least mean square (LMS) statistic toimplement the vector correlator and determines the derotation factorsfor each multipath component from the received multipath signal. The AVCof FIG. 8 c is similar to the exemplary implementation of the Pilot AVCused to despread the pilot spreading code shown in FIG. 7. The digitalphase locked loop 721 is replaced by the phase locked loop 850 havingvoltage controlled oscillator 851, loop filter 852, limiter 853 andimaginary component separator 854. The difference between the correcteddespread output signal ido and an ideal despread output signal isprovided by adder 855, and the difference signal is a despread errorvalue ide which is further used by the derotation circuits to compensatefor errors in the derotation factors.

In a multipath signal environment, the signal energy of a transmittedsymbol is spread out over the multipath signal components. The advantageof multipath signal addition is that a substantial portion of signalenergy is recovered in an output signal from the AVC. Consequently, adetection circuit has an input signal from the AVC with a highersignal-to-noise ratio (SNR), and so can detect the presence of a symbolwith a lower bit-error ratio (BER). In addition, measuring the output ofthe AVC is a good indication of the transmit power of the transmitter,and a good measure of the system's interference noise.

XIX. Adaptive Matched Filter

One embodiment of the current invention includes an adaptive matchedfilter (AMF) to optimally combine the multipath signal components in areceived spread spectrum message signal. The AMF is a tapped delay linewhich holds shifted values of the sampled message signal and combinesthese after correcting for the channel response. The correction for thechannel response is done using the channel response estimate calculatedin the AVC which operates on the pilot sequence signal. The outputsignal of the AMF is the combination of the multipath components whichare summed to give a maximum value. This combination corrects for thedistortion of multipath signal reception. The various messagedespreading circuits operate on this combined multipath component signalfrom the AMF.

FIG. 8 d shows an exemplary embodiment of the AMF. The sampled signalfrom the A/D converter 870 is applied to the L-stage delay line 872.Each stage of this delay line 872 holds the signal corresponding to adifferent multipath signal component. Correction for the channelresponse is applied to each delayed signal component by multiplying thecomponent in the respective multiplier of multiplier bank 874 with therespective weighting factor w₁, w₂, . . . , w_(L) from the AVCcorresponding to the delayed signal component. All weighted signalcomponents are summed in the adder 876 to give the combined multipathcomponent signal y(t).

The combined multipath component signal y(t) does not include thecorrection due to phase and frequency offset of the carrier signal. Thecorrection for the phase and frequency offset of the carrier signal ismade to y(t) by multiplying y(t) with carrier phase and frequencycorrection (derotation phasor) in multiplier 878. The phase andfrequency correction is produced by the AVC as described previously.FIG. 8 d shows the correction as being applied before the despreadingcircuits 880, but alternate embodiments of the invention can apply thecorrection after the despreading circuits.

XX. Method to Reduce Re-Acquisition Time with Virtual Location

One consequence of determining the difference in code phase between thelocally generated pilot code sequence and a received spreading codesequence is that an approximate value for the distance between the basestation and a subscriber unit can be calculated. If the SU has arelatively fixed position with respect to the RCS of the base station,the uncertainty of received spreading code phase is reduced forsubsequent attempts at re-acquisition by the SU or RCS. The timerequired for the base station to acquire the access signal of a SU thathas gone “off-hook” contributes to the delay between the SU goingoff-hook and the receipt of a dial tone from the PSTN. For systems thatrequire a short delay, such as 150 msec for dial tone after off-hook isdetected, a method which reduces the acquisition and bearer channelestablishment time is desirable. One embodiment of the present inventionuses such a method of reducing re-acquisition by use of virtuallocating. Additional details of this technique are described in U.S.Pat. No. 5,940,382 entitled “Virtual Locating of a Fixed Subscriber Unitto Reduce Re-Acquisition Time” by John W. Haim, which is incorporatedherein by reference.

The RCS acquires the SU CDMA signal by searching only those receivedcode phases corresponding to the largest propagation delay of theparticular system. In other words, the RCS assumes that all SUs are at apredetermined, fixed distance from the RCS. The first time the SUestablishes a channel with the RCS, the normal search pattern isperformed by the RCS to acquire the access channel. The normal methodstarts by searching the code phases corresponding to the longestpossible delay, and gradually adjusts the search to the code phases withthe shortest possible delay. However, after the initial acquisition, theSU can calculate the delay between the RCS and the SU by measuring thetime difference between sending a short access message to the RCS andreceiving an acknowledgment message, and using the received global pilotchannel as a timing reference. The SU can also receive the delay valueby having the RCS calculate the round trip delay difference from thecode phase difference between the global pilot code generated at the RCSand the received assigned pilot sequence from the SU, and then sendingthe SU the value on a predetermined control channel. Once the round tripdelay is known to the SU, the SU may adjust the code phase of thelocally generated assigned pilot and spreading code sequences by addingthe delay required to make the SU appear to the RCS to be at thepredetermined fixed distance from the RCS. Although the method isexplained for the largest delay, a delay corresponding to anypredetermined location in the system can be used.

A second advantage of the method of reducing re-acquisition by virtuallocating is that a conservation in SU power use can be achieved. Notethat a SU that is “powered down” or in a sleep mode needs to start thebearer channel acquisition process with a low transmit power level andramp-up power until the RCS can receive its signal in order to minimizeinterference with other users. Since the subsequent re-acquisition timeis shorter, and because the SU's location is relatively fixed inrelation to the RCS, the SU can ramp-up transmit power more quicklybecause the SU will wait a shorter period of time before increasingtransmit power. The SU waits a shorter period because it knows, within asmall error range, when it should receive a response from the RCS if theRCS has acquired the SU signal.

XXI. The Radio Carrier Station (RCS)

The Radio Carrier Station (RCS) of the present invention acts as acentral interface between the SU and the remote processing controlnetwork element, such as a radio distribution unit (RDU). The interfaceto the RDU of the present embodiment follows the G.704 standard and aninterface according to a modified version of DECT V5.1, but the presentinvention can support any interface that can exchange call control andtraffic channels. The RCS receives information channels from the RDUincluding call control data, and traffic channel data such as, but notlimited to, 32 kb/s ADPCM, 64 kb/s PCM and ISDN, as well as systemconfiguration and maintenance data. The RCS also terminates the CDMAradio interface bearer channels with SUs, which channels include bothcontrol data, and traffic channel data. In response to the call controldata from either the RDU or a SU, the RCS allocates traffic channels tobearer channels on the RF communication link and establishes acommunication connection between the SU and the telephone networkthrough an RDU.

As shown in FIG. 9, the RCS receives call control and messageinformation data into the MUXs 905, 906 and 907 through interface lines901, 902 and 903. Although E1 format is shown, other similartelecommunication formats can be supported in the same manner asdescribed below. The MUXs shown in FIG. 9 may be implemented usingcircuits similar to that shown in FIG. 10. The MUX shown in FIG. 10includes system clock signal generator 1001 consisting of phase lockedoscillators (not shown) which generate clock signals for the line PCMhighway 1002 (which is part of PCM highway 910), and high speed bus(HSB) 970; and the MUX controller 1010 which synchronizes the systemclock 1001 to interface line 1004. It is contemplated that the phaselock oscillators can provide timing signals for the RCS in the absenceof synchronization to a line. The MUX line interface 1011 separates thecall control data from the message information data. Referring to FIG.9, each MUX provides a connection to the wireless access controller(WAC) 920 through the PCM highway 910. The MUX controller 1010 alsomonitors the presence of different tones present in the informationsignal by means of tone detector 1030. Additionally, the MUX Controller1010 provides the ISDN D channel network signaling locally to the RDU.

The MUX line interface 1011, such as a FALC 54, includes an E1 interface1012 which consists of a transmit connection pair (not shown) and areceive connection pair (not shown) of the MUX connected to the RDU orcentral office (CO) ISDN switch at the data rate of 2.048 Mbps. Thetransmit and receive connection pairs are connected to the E1 interface1012 which translates differential tri-level transmit/receive encodedpairs into levels for use by the framer 1015. The line interface 1011uses internal phase-locked-loops (not shown) to produce E1-derived 2.048MHz and 4.096 MHz clocks as well as an 8 KHz frame-sync pulse. The lineinterface can operate in clock-master or clock-slave mode. While theexemplary embodiment is shown as using an E1 interface, it iscontemplated that other types of telephone lines which convey multiplecalls may be used, for example, T1 lines or lines which interface to aprivate branch exchange (PBX).

The line interface framer 1015 frames the data streams by recognizingthe framing patterns on channel-1 (time-slot 0) of the incoming line,inserts and extracts service bits and generates/checks line servicequality information.

As long as a valid E1 signal appears at the E1 interface 1012, the FALC54, recovers a 2.048 MHz PCM clock signal from the E1 line. This clock,via system clock 1001, is used system wide as a PCM highway clocksignal. If the E1 line fails, the FALC 54 continues to deliver a PCMclock derived from an oscillator signal o(t) connected to the sync input(not shown) of the FALC 54. This PCM clock serves the RCS system untilanother MUX with an operational E1 line assumes responsibility forgenerating the system clock signals.

The framer 1015 generates a received frame sync pulse, which in turn canbe used to trigger the PCM Interface 1016 to transfer data onto the linePCM highway 1002 and into the RCS system for use by other elements.Since all E1 lines are frame synchronized, all line PCM highways arealso frame synchronized. From this 8 KHz PCM Sync pulse, the systemclock signal generator 1001 of the MUX uses a phase locked loop (notshown) to synthesize the PN×2 clock (e.g., 15.96 MHz)(W₀(t)). Thefrequency of this clock signal is different for different transmissionbandwidths as described in Table 7.

The MUX includes a MUX controller 1010, such as a 25 MHz quad integratedcommunications controller, containing a microprocessor 1020, programmemory 1021, and time division multiplexer (TDM) 1022. The TDM 1022 iscoupled to receive the signal provided by the framer 1015, and extractsinformation placed in time slots 0 and 16. The extracted informationgoverns how the MUX controller 1010 processes the link access protocol−D(LAPD) data link. The call control and bearer modification messages,such as those defined as V5.1 network layer messages, are either passedto the WAC, or used locally by the MUX controller 1010.

The RCS line PCM highway 1002 is connected to and originates with theframer 1015 through PCM Interface 1016, and is comprised of a 2.048 MHzstream of data in both the transmit and receive direction. The RCS alsocontains a high speed bus (HSB) 970 which is the communication linkbetween the MUX, WAC, and MIUs. The HSB 970 supports a data rate of, forexample, 100 Mbit/sec. Each of the MUX, WAC, and MIU access the HSBusing arbitration. The RCS of the present invention also can includeseveral MUXs requiring one board to be a “master” and the rest “slaves”.Details on the implementation of the HSB may be found in U.S. Pat. No.5,754,803 entitled “Parallel Packetized Intermodule Arbitrated HighSpeed Control and Data Bus” by Robert T. Regis, which is incorporatedherein by reference.

Referring to FIG. 9, the wireless access controller (WAC) 920 is the RCSsystem controller which manages call control functions andinterconnection of data streams between the MUXs 905, 906, 907, modeminterface units (MIUs) 931, 932, 933. The WAC 920 also controls andmonitors other RCS elements such as the VDC 940, RF 950, and poweramplifiers 960. The WAC 920 as shown in FIG. 11, allocates bearerchannels to the modems on each MIU 931, 932, 933 and allocates themessage data on line PCM Highway 910 from the MUXs 905, 906, 907 to themodems on the MIUs 931, 932, 933. This allocation is made through theSystem PCM Highway 911 by means of a time slot interchange on the WAC920. If more than one WAC is present for redundancy purposes, the WACsdetermine the master-slave relationship with a second WAC. The WAC 920also generates messages and paging information responsive to callcontrol signals from the MUXs 905, 906, 907 received from a remoteprocessor, such as an RDU; generates broadcast data which is transmittedto the MIU master modem 934; and controls the generation by the MIU MM934 of the Global system Pilot spreading code sequence. The WAC 920 alsois connected to an external network manager (NM) 980 for craftsperson oruser access.

Referring to FIG. 11, the WAC includes a time-slot interchanger (TSI)1101 which transfers information from one time slot in a line PCMhighway or system PCM highway to another time slot in either the same ordifferent line PCM highway or system PCM highway. The TSI 1101 isconnected to the WAC controller 1111 of FIG. 11 which controls theassignment or transfer of information from one time slot to another timeslot and stores this information in memory 1120. The exemplaryembodiment of the invention has four PCM Highways 1102, 1103, 1104, 1105connected to the TSI. The WAC also is connected to the HSB 970, throughwhich WAC communicates to a second WAC (not shown), to the MUXs and tothe MIUs.

Referring to FIG. 11, the WAC 920 includes a WAC controller 1111employing, for example, a microprocessor 1112, such as a Motorola MC68040 and a communications processor 1113, such as the Motorola MC68360QUICC communications processor, and a clock oscillator 1114 whichreceives a clock synch signal wo(t) from the system clock generator. Theclock generator is located on a MUX (not shown) to provide timing to theWAC controller 1111. The WAC controller 1111 also includes memory 1120including flash PROM 1121 and SRAM memory 1122. The flash PROM 1121contains the program code for the WAC controller 1111 and isreprogrammable for new software programs downloaded from an externalsource. The SRAM 1122 is provided to contain the temporary data writtento and read from memory 1120 by the WAC controller 1111.

A low speed bus 912 is connected to the WAC 920 for transferring controland status signals between the RF transmitter/receiver 950, VDC 940, RF950 and power amplifier 960 as shown in FIG. 9. The control signals aresent from the WAC 920 to enable or disable the RF transmitters/receiver950 or power amplifier 960, and the status signals are sent from the RFtransmitters/receiver 950 or power amplifier 960 to monitor the presenceof a fault condition.

The exemplary RCS contains at least one MIU 931, which is shown in FIG.12 and now described in detail. The MIU of the exemplary embodimentincludes six CDMA modems, but the invention is not limited to thisnumber of modems. The MIU includes a system PCM highway 1201 connectedto each of the CDMA Modems 1210, 1211, 1212, 1215 through a PCMInterface 1220, a control channel bus 1221 connected to MIU controller1230 and each of the CDMA modems 1210, 1211, 1212, 1215, an MIU clocksignal generator (CLK) 1231, and a modem output combiner 1232. The MIUprovides the RCS with the following functions: the MIU controllerreceives CDMA channel assignment instructions from the WAC and assigns amodem to a user information signal which is applied to the lineinterface of the MUX and a modem to receive the CDMA channel from theSU; it also combines the CDMA transmit modem data for each of the MIUCDMA modems; multiplexes I and Q transmit message data from the CDMAmodems for transmission to the VDC; receives analog I and Q receivemessage data from the VDC; distributes the I and Q data to the CDMAmodems; transmits and receives digital AGC data; distributes the AGCdata to the CDMA modems; and sends MIU board status and maintenanceinformation to the WAC 920.

The MIU controller 1230 of the exemplary embodiment of the presentinvention contains one communication microprocessor 1240, such as theMC68360 “QUICC” processor, and includes a memory 1242 having a FlashPROM memory 1243 and a SRAM memory 1244. Flash PROM 1243 is provided tocontain the program code for the microprocessors 1240, and the memory1243 is downloadable and reprogrammable to support new program versions.SRAM 1244 is provided to contain the temporary data space needed by theMC68360 microprocessor 1240 when the MIU controller 1230 reads or writesdata to memory

The MIU CLK circuit 1231 provides a timing signal to the MIU controller1230, and also provides a timing signal to the CDMA modems. The MIU CLKcircuit 1231 receives, and is synchronized to, the system clock signalwo(t). The controller clock signal generator 1213 also receives andsynchronizes to the spreading code clock signal pn(t) which isdistributed to the CDMA modems 1210, 1211, 1212, 1215 from the MUX.

The RCS of the present embodiment includes a system modem 1210 containedon one MIU. The system modem 1210 includes a broadcast spreader (notshown) and a pilot generator (not shown). The broadcast modem providesthe broadcast information used by the exemplary system, and thebroadcast message data is transferred from the MIU controller 1230 tothe system modem 1210. The system modem also includes four additionalmodems (not shown) which are used to transmit the signals CT1 throughCT4 and AX1 through AX4. The system modem 1210 provides unweighted I andQ broadcast message data signals which are applied to the VDC. The VDCadds the broadcast message data signal to the MIU CDMA modem transmitdata of all CDMA modems 1210, 1211, 1212, 1215 and the global pilotsignal.

The pilot generator (PG) 1250 provides the global pilot signal which isused by the present invention, and the global pilot signal is providedto the CDMA modems 1210, 1211, 1212, 1215 by the MIU controller 1230.However, other embodiments of the present invention do not require theMIU controller to generate the global pilot signal, but include a globalpilot signal generated by any form of CDMA code sequence generator. Inthe described embodiment of the invention, the unweighted I and Q globalpilot signal is also sent to the VDC where it is assigned a weight, andadded to the MIU CDMA modem transmit data and broadcast message datasignal.

System timing in the RCS is derived from the E1 interface. There arefour MUXs in an RCS, three of which (905, 906 and 907) are shown in FIG.9. Two MUXs are located on each chassis. One of the two MUXs on eachchassis is designated as the master, and one of the masters isdesignated as the system master. The MUX which is the system masterderives a 2.048 MHz PCM clock signal from the E1 interface using aphase-locked loop (not shown). In turn, the system master MUX dividesthe 2.048 MHz PCM clock signal in frequency by 16 to derive a 128 KHzreference clock signal. The 128 KHz reference clock signal isdistributed from the MUX that is the system master to all the otherMUXs. In turn, each MUX multiplies the 128 KHz reference clock signal infrequency to synthesize the system clock signal which has a frequencythat is twice the frequency of the PN-clock signal. The MUX also dividesthe 128 KHz clock signal in frequency by 16 to generate the 8 KHz framesynch signal which is distributed to the MIUs. The system clock signalfor the exemplary embodiment has a frequency of 11.648 MHz for a 7 MHzbandwidth CDMA channel. Each MUX also divides the system clock signal infrequency by 2 to obtain the PN-clock signal and further divides thePN-clock signal in frequency by 29 877 120 (the PN sequence length) togenerate the PN-synch signal which indicates the epoch boundaries. ThePN-synch signal from the system master MUX is also distributed to allMUXs to maintain phase alignment of the internally generated clocksignals for each MUX. The PN-synch signal and the frame synch signal arealigned. The two MUXs that are designated as the master MUXs for eachchassis then distribute both the system clock signal and the PN-clocksignal to the MIUs and the VDC.

The PCM highway interface 1220 connects the system PCM highway 911 toeach CDMA modem 1210, 1211, 1212, 1215. The WAC controller transmitsmodem control information, including traffic message control signals foreach respective user information signal to the MIU controller 1230through the HSB 970. Each CDMA modem 1210, 1211, 1212, 1215 receives atraffic message control signal, which includes signaling information,from the MIU controller 1111. Traffic message control signals alsoinclude call control (CC) information and spreading code and despreadingcode sequence information.

The MIU also includes the transmit data combiner 1232 which addsweighted CDMA modem transmit data including in-phase (I) and quadrature(Q) modem transmit data from the CDMA modems 1210, 1211, 1212, 1215 onthe MIU. The I modem transmit data is added separately from the Q modemtransmit data. The combined I and Q modem transmit data output signal ofthe transmit data combiner 1232 is applied to the I and Q multiplexer1233 that creates a single CDMA transmit message channel composed of theI and Q modem transmit data multiplexed into a digital data stream.

The receiver data input Circuit (RDI) 1234 receives the analogdifferential I and Q Data from the video distribution circuit (VDC) 940shown in FIG. 9 and distributes analog differential I and Q data to eachof the CDMA modems 1210, 1211, 1212, 1215 of the MIU. The automatic gaincontrol (AGC) distribution circuit 1235 receives the AGC data signalfrom the VDC and distributes the AGC data to each of the CDMA modems ofthe MIU. The TRL circuit 1233 receives the traffic lights informationand similarly distributes the Traffic light data to each of the Modems1210, 1211, 1212, 1215.

XXII. The CDMA Modem

The CDMA modem provides for generation of CDMA spreading code sequencesand synchronization between transmitter and receiver. It also providesfour full duplex channels (TR0, TR1, TR2, TR3) programmable to 64, 32,16, and 8 ksym/sec. each, for spreading and transmission at a specificpower level. The CDMA modem measures the received signal strength toallow automatic power control, it generates and transmits pilot signals,and encodes and decodes using the signal for forward error correction(FEC). The modem in an SU also performs transmitter spreading code pulseshaping using an FIR filter. The CDMA modem is also used by thesubscriber unit (SU), and in the following discussion those featureswhich are used only by the SU are distinctly pointed out. The operatingfrequencies of the CDMA modem are given in Table 10. TABLE 10 OperatingFrequencies Bandwidth Chip Rate Symbol Rate Gain (MHz) (MHz) (KHz)(Chips/Symbol) 7 5.824 64 91 10 8.320 64 130 10.5 8.512 64 133 14 11.64864 182 15 12.480 64 195

Each CDMA modem 1210, 1211, 1212, 1215 of FIG. 12, and as shown in FIG.13, is composed of a transmit section 1301 and a receive section 1302.Also included in the CDMA modem is a control center 1303 which receivescontrol messages CNTRL from the external system. These messages areused, for example, to assign particular spreading codes, activate thespreading or despreading or to assign transmission rates. In addition,the CDMA modem has a code generator means 1304 used to generate thevarious spreading and despreading codes used by the CDMA modem. Thetransmit section 1301 is for transmitting the input information andcontrol signals m_(i)(t), i=1, 2, . . . I as spread-spectrum processeduser information signals sc_(j)(t), j=1, 2, . . . J. The transmitsection 1301 receives the global pilot code from the code generator 1304which is controlled by the control means 1303. The spread spectrumprocessed user information signals are ultimately added to other similarprocessed signals and transmitted as CDMA channels over the CDMA RFforward message link, for example to the SUs. The receive section 1302receives CDMA channels as r(t) and despreads and recovers the userinformation and control signals rc_(k)(t), k=1, 2, . . . K transmittedover the CDMA RF reverse message link, for example to the RCS from theSUs.

XXIII. CDMA Modem Transmitter Section

Referring to FIG. 14, the code generator means 1304 includes transmittiming control logic 1401 and spreading code PN-generator 1402, and thetransmit section 1301 includes modem input signal receiver (MISR) 1410,convolution encoders 1411, 1412, 1413, 1414, spreaders 1420, 1421, 1422,1423, 1424 and combiner 1430. The transmit section 1301 receives themessage data channels MESSAGE, convolutionally encodes each message datachannel in the respective convolutional encoder 1411, 1412, 1413, 1414,modulates the data with random spreading code sequence in the respectivespreader 1420, 1421, 1422, 1423, 1424, and combines modulated data fromall channels, including the pilot code received in the describedembodiment from the code generator, in the combiner 1430 to generate Iand Q components for RF transmission. The transmitter section 1301 ofthe present embodiment supports four (TR0, TR1, TR2, TR3) 64, 32, 16, 8kb/s programmable channels. The message channel data is a timemultiplexed signal received from the PCM highway 1201 through PCMinterface 1220 and input to the MISR 1410.

FIG. 15 is a block diagram of an exemplary MISR 1410. For the exemplaryembodiment of the present invention, a counter is set by the 8 KHz framesynchronization signal MPCMSYNC and is incremented by 2.048 MHz MPCMCLKfrom the timing circuit 1401. The counter output is compared bycomparator 1502 against TRCFG values corresponding to slot time locationfor TR0, TR1, TR2, TR3 message channel data; and the TRCFG values arereceived from the MIU controller 1230 in MCTRL. The comparator sendscount signal to the registers 1505, 1506, 1507 and 1508 which clocksmessage channel data into buffers 1510, 1511, 1512, 1513 using theTXPCNCLK timing signal derived from the system clock. The message datais provided from the signal MSGDAT from the PCM highway signal MESSAGEwhen enable signals TR0EN, TR1EN, TR2EN and TR3EN from timing controllogic 1401 are active. In further embodiments, MESSAGE may also includesignals that enable registers depending upon an encryption rate or datarate. If the counter output is equal to one of the channel locationaddresses, the specified transmit message data in registers 1510, 1511,1512, 1513 are input to the convolutional encoders 1411, 1412, 1413,1414 shown in FIG. 14.

The convolutional encoder enables the use of forward error correction(FEC) techniques, which are well known in the art. FEC techniques dependon introducing redundancy in generation of data in encoded form. Encodeddata is transmitted and the redundancy in the data enables the receiverdecoder device to detect and correct errors. One embodiment of thepresent invention employs convolutional encoding. Additional data bitsare added to the data in the encoding process and are the codingoverhead. The coding rate is expressed as the ratio of data bitstransmitted to the total bits (code data+redundant data) transmitted andis called the rate “R” of the code.

Convolution codes are codes where each code bit is generated by theconvolution of each new uncoded bit with a number of previously codedbits. The total number of bits used in the encoding process is referredto as the constraint length, “K”, of the code. In convolutional coding,data is clocked into a shift register of K bits length so that anincoming bit is clocked into the register, and it and the existing K−1bits are convolutionally encoded to create a new symbol. The convolutionprocess consists of creating a symbol consisting of a modulo-2 sum of acertain pattern of available bits, always including the first bit andthe last bit in at least one of the symbols.

FIG. 16 shows the block diagram of a K=7, R=1/2 convolution encodersuitable for use as the encoder 1411 shown in FIG. 14. This circuitencodes the TR0 channel as used in one embodiment of the presentinvention. Seven-bit register 1601 with stages Q1 through Q7 uses thesignal TXPNCLK to clock in TR0 data when the TR0EN signal is asserted.The output value of stages Q1, Q2, Q3, Q4, Q6, and Q7 are each combinedusing EXCLUSIVE-OR Logic 1602, 1603 to produce respective I and Qchannel FEC data for the TR0 channel FECTR0DI and FECTR0DQ.

Two output symbol streams FECTR0DI and FECTR0DQ are generated. TheFECTR0DI symbol stream is generated by EXCLUSIVE-OR logic 1602 of shiftregister outputs corresponding to bits 6, 5, 4, 3, and 0, (Octal 171)and is designed as In phase component “I” of the transmit messagechannel data. The symbol stream FECTR0DQ is likewise generated byEXCLUSIVE-OR logic 1603 of shift register outputs from bits 6, 4, 3, 1and 0, (Octal 133) and is designated as Quadrature component “Q” of thetransmit message channel data. Two symbols are transmitted to representa single encoded bit creating the redundancy necessary to enable errorcorrection to take place on the receiving end.

Referring to FIG. 14, the shift enable clock signal for the transmitmessage channel data is generated by the control timing logic 1401. Theconvolutionally encoded transmit message channel output data for eachchannel is applied to the respective spreader 1420, 1421, 1422, 1423,1424 which multiplies the transmit message channel data by itspreassigned spreading codesequence from code generator 1402. Thisspreading code sequence is generated by control 1303 as previouslydescribed, and is called a random pseudonoise signature code (PN-code).

The output signal of each spreader 1420, 1421, 1422, 1423, 1424 is aspread transmit data channel. The operation of the spreader is asfollows: the spreading of channel output (I+jQ) multiplied by a randomsequence (PNI+jPNQ) yields the in-phase component I of the result beingcomposed of (I xor PNI) and (−Q xor PNQ). Quadrature component Q of theresult is (Q xor PNI) and (I xor PNQ). Since there is no channel datainput to the pilot channel logic (I=1, Q values are prohibited), thespread output signal for pilot channels yields the respective sequencesPNI for I component and PNQ for Q component.

The combiner 1430 receives the I and Q spread transmit data channels andcombines the channels into an I modem transmit data signal (TXIDAT) anda Q modem transmit data signal (TXQDAT). The I-spread transmit data andthe Q-spread transmit data are added separately.

For an SU, the CDMA modem transmit section 1301 includes the FIR filtersto receive the I and Q channels from the combiner to provide pulseshaping, close-in spectral control and x/sin (x) correction for thetransmitted signal. Separate but identical FIR filters receive the I andQ spread transmit data streams at the chipping rate, and the outputsignal of each of the filters is at twice the chipping rate. Theexemplary FIR filters are 28 tap even symmetrical filters, whichupsample (interpolate) by 2. The upsampling occurs before the filtering,so that 28 taps refers to 28 taps at twice the chipping rate, and theupsampling is accomplished by setting every other sample to zero.Exemplary coefficients are shown in Table 11. TABLE 11 CoefficientValues Coeff. No.: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Value: 3 −11 −34 −2219 17 −32 −19 52 24 −94 −31 277 468 Coeff. No.: 14 15 16 17 18 19 20 2122 24 25 26 27 Value 277 −31 −94 24 52 −19 −32 17 19 −22 −34 −11 3

XXIV. CDMA Modem Receiver Section

Referring to FIGS. 9 and 12, the RF receiver 950 of the presentembodiment accepts analog input I and Q CDMA channels, which aretransmitted to the CDMA modems 1210, 1211, 1212, 1215 through the MIUs931, 932, 933 from the VDC 940. These I and Q CMDA channel signals aresampled by the CDMA modem receive section 1302 (shown in FIG. 13) andconverted to I and Q digital receive message signals using an analog todigital (A/D) converter 1730, shown in FIG. 17. The sampling rate of theA/D converter of the exemplary embodiment of the present invention isequivalent to the despreading code rate. The I and Q digital receivemessage signals are then despread with correlators using six differentcomplex spreading code sequences corresponding to the despreading codesequences of the four channels (TR0, TR1, TR2, TR3), APC information andthe pilot code.

Time synchronization of the receiver to the received signal is separatedinto two phases; there is an initial acquisition phase and then atracking phase after the signal timing has been acquired. The initialacquisition is done by shifting the phase of the locally generated pilotcode sequence relative to the received signal and comparing the outputof the pilot despreader to a threshold. The method used is calledsequential search. Two thresholds (match and dismiss) are calculatedfrom the auxiliary despreader. Once the signal is acquired, the searchprocess is stopped and the tracking process begins. The tracking processmaintains the code generator 1304 (shown in FIGS. 13 and 17) used by thereceiver in synchronization with the incoming signal. The tracking loopused is the delay-locked loop (DLL) and is implemented in theacquisition & track 1701 and the IPM 1702 blocks of FIG. 17.

In FIG. 13, the modem controller 1303 implements the phase lock loop(PLL) as a software algorithm in SW PLL logic 1724 of FIG. 17 thatcalculates the phase and frequency shift in the received signal relativeto the transmitted signal. The calculated phase shifts are used toderotate the phase shifts in rotate and combine blocks 1718, 1719, 1720,1721 of the multipath data signals for combining to produce outputsignals corresponding to receive channels TR0′, TR1′, TR2′, TR3′. Thedata is then Viterbi decoded in Viterbi decoders 1713, 1714, 1715, 1716to remove the convolutional encoding in each of the received messagechannels.

FIG. 17 indicates that the Code Generator 1304 provides the codesequences Pn_(i)(t), i=1, 2, . . . I used by the receive channeldespreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709. The code sequencesgenerated are timed in response to the SYNK signal of the system clocksignal and are determined by the CCNTRL signal from the modem controller1303 shown in FIG. 13. Referring to FIG. 17, the CDMA modem receiversection 1302 includes adaptive matched filter (AMF) 1710, channeldespreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709, pilot AVC 1711,auxiliary AVC 1712, Viterbi decoders 1713, 1714, 1715, 1716, modemoutput interface (MOI) 1717, rotate and combine logic 1718, 1719, 1720,1721, AMF weight generator 1722, and quantile estimation logic 1723 and1733.

In another embodiment of the invention, the CDMA modem receiver alsoincludes a bit error integrator to measure the BER of the channel andidle code insertion logic between the Viterbi decoders 1713, 1714, 1715,1716 and the MOI 1717 to insert idle codes in the event of loss of themessage data.

The AMF 1710 resolves multipath interference introduced by the airchannel. The exemplary AMF 1710 uses an 11 stage complex FIR filter asshown in FIG. 18. The received I and Q digital message signals arereceived at the register 1820 from the A/D 1730 of FIG. 17 and aremultiplied in multipliers 1801, 1802, 1803, 1810, 1811 by I and Qchannel weights W1 to W11 received from AMF weight generator 1722 ofFIG. 17. In the exemplary embodiment, the A/D 1730 provides the I and Qdigital receive message signal data as 2's complement values, 6 bits forI and 6 bits for Q which are clocked through an 11 stage shift register1820 responsive to the receive spreading-code clock signal RXPNCLK. Thesignal RXPNCLK is generated by the timing section 1401 of codegeneration logic 1304. Each stage of the shift register is tapped andcomplex multiplied in the multipliers 1801, 1802, 1803, 1810, 1811 byindividual (6-bit I and 6-bit Q) weight values to provide 11tap-weighted products which are summed in adder 1830, and limited to7-bit I and 7-bit Q values.

The CDMA modem receive section 1302 (shown in FIG. 13) providesindependent channel despreaders 1703, 1704, 1705, 1706, 1707, 1708, 1709(shown in FIG. 17) for despreading the message channels. The describedembodiment despreads 7 message channels, each despreader accepting a1-bit I by 1-bit Q despreading code signal to perform a complexcorrelation of this code against a 8-bit I by 8-bit Q data input. The 7despreaders correspond to the 7 channels: traffic channel 0 (TR0′),TR1′, TR2′, TR3′, AUX (a spare channel), APC and pilot (PLT).

The pilot AVC 1711 shown in FIG. 19 receives the I and Q pilot spreadingcode sequence values PCI and PCQ into shift register 1920 responsive tothe timing signal RXPNCLK, and includes 11 individual despreaders 1901through 1911 each correlating the I and Q digital receive message signaldata with a one chip delayed version of the same pilot code sequence.Signals OE1, OE2, . . . OE11 are used by the modem control 1303 toenable the despreading operation. The output signals of the despreadersare combined in combiner 1920 forming correlation signal DSPRDAT of thePilot AVC 1711, which is received by the ACQ & track logic 1701 (shownin FIG. 17), and ultimately by modem controller 1303 (shown in FIG. 13).The ACQ & track logic 1701 uses the correlation signal value todetermine if the local receiver is synchronized with its remotetransmitter.

The auxiliary AVC 1712 also receives the I and Q digital receive messagesignal data and, in the described embodiment, includes four separatedespreaders 2001, 2002, 2003, 2004 as shown in FIG. 20. Each despreaderreceives and correlates the I and Q digital receive message data withdelayed versions of the same despreading code sequence PARI and PARQwhich are provided by code generator 1304 input to and contained inshift register 2020. The output signals of the despreaders 2001, 2002,2003, 2004 are combined in combiner 2030 which provides noisecorrelation signal ARDSPRDAT. The auxiliary AVC spreading code sequencedoes not correspond to any transmit spreading code sequence of thesystem. Signals OE1, OE2, . . . OE4 are used by the modem control 1303to enable the despreading operation. The Auxiliary AVC 1712 provides anoise correlation signal ARDSPRDAT from which quantile estimates arecalculated by the quantile estimator 1733, and provides a noise levelmeasurement to the ACQ & Track logic 1701 (shown in FIG. 17) and modemcontroller 1303 (shown in FIG. 13).

Each despread channel output signal corresponding to the receivedmessage channels TR0′, TR1′, TR2′, and TR3′ is input to a correspondingViterbi decoder 1713, 1714, 1715, 1716 shown in FIG. 17 which performsforward error correction on convolutionally encoded data. The Viterbidecoders of the exemplary embodiment have a constraint length of K=7 anda rate of R=1/2. The decoded despread message channel signals aretransferred from the CDMA modem to the PCM Highway 1201 through the MOI1717. The operation of the MOI is essentially the same as the operationof the MISR of the transmit section 1301 (shown in FIG. 13) except inreverse.

The CDMA modem receiver section 1302 implements several differentalgorithms during different phases of the acquisition, tracking anddespreading of the receive CDMA message signal.

When the received signal is momentarily lost (or severely degraded) theidle code insertion algorithm inserts idle codes in place of the lost ordegraded receive message data to prevent the user from hearing loudnoise bursts on a voice call. The idle codes are sent to the MOI 1717(shown in FIG. 17) in place of the decoded message channel output signalfrom the Viterbi decoders 1713, 1714, 1715, 1716. The idle code used foreach traffic channel is programmed by the Modem Controller 1303 bywriting the appropriate pattern IDLE to the MOI, which in the presentembodiment is a 8 bit word for a 64 kb/s stream, 4 bit word for a 32kb/s stream.

XXV. Modem Algorithms for Acquisition and Tracking of Received PilotSignal

The acquisition and tracking algorithms are used by the receiver todetermine the approximate code phase of a received signal, synchronizethe local modem receiver despreaders to the incoming pilot signal, andtrack the phase of the locally generated pilot code sequence with thereceived pilot code sequence. Referring to FIGS. 13 and 17, thealgorithms are performed by the modem controller 1303, which providesclock adjust signals to code generator 1304. These adjust signals causethe code generator for the despreaders to adjust locally generated codesequences in response to measured output values of the pilot rake 1711and quantile values from estimation logic 1733. Quantile values arenoise statistics measured from the in-phase and quadrature channels fromthe output values of the AUX vector correlator 1712 (shown in FIG. 17).Synchronization of the receiver to the received signal is separated intotwo phases; an initial acquisition phase and a tracking phase. Theinitial acquisition phase is accomplished by clocking the locallygenerated pilot spreading code sequence at a higher or lower rate thanthe received signal's spreading code rate, sliding the locally generatedpilot spreading code sequence and performing sequential probabilityratio test (SPRT) on the output of the pilot vector correlator 1711. Thetracking phase maintains the locally generated spreading code pilotsequence in synchronization with the incoming pilot signal. Details ofthe quantile estimation logic 1723 and 1733 may be found in U.S. Pat.No. 5,535,238 entitled “Spread Spectrum Adaptive Power ControlCommunications System and Method” by Donald L. Schilling et al., whichis incorporated by reference herein.

The SU cold acquisition algorithm is used by the SU CDMA modem when itis first powered up, and therefore has no knowledge of the correct pilotspreading code phase, or when an SU attempts to reacquiresynchronization with the incoming pilot signal but has taken anexcessive amount of time. The cold acquisition algorithm is divided intotwo sub-phases. The first subphase consists of a search over the length233415 code used by the FBCH. Once this sub-code phase is acquired, thepilot's 233415×128 length code is known to within an ambiguity of 128possible phases. The second subphase is a search of these remaining 128possible phases. In order not to lose synch with the FBCH, in the secondphase of the search, it is desirable to switch back and forth betweentracking of the FBCH code and attempting acquisition of the pilot code.

The RCS acquisition of short access pilot (SAXPT) algorithm is used byan RCS CDMA modem to acquire the SAXPT pilot signal of an SU. Additionaldetails of this technique are described in U.S. Pat. No. 5,841,768entitled “Method of Controlling Initial Power Ramp-up in CDMA Systems byUsing Short Codes” by Fatih M. Ozluturk et al., which is incorporatedherein by reference. The algorithm is a fast search algorithm becausethe SAXPT is a short code sequence of length N, where N=chips/symbol,and ranges from 45 to 195, depending on the system's bandwidth. Thesearch cycles through all possible phases until acquisition is complete.

The RCS acquisition of the long access pilot (LAXPT) algorithm beginsimmediately after acquisition of SAXPT. The SU's code phase is knownwithin a multiple of a symbol duration, so in the exemplary embodimentof the invention there may be 7 to 66 phases to search within the roundtrip delay from the RCS. This boundary is a result of the SU pilotsignal being synchronized to the RCS global pilot signal.

The re-acquisition algorithm begins when loss of lock (LOL) occurs. AZ-search algorithm is used to speed the process on the assumption thatthe code phase has not drifted far from where it was the last time thesystem was locked. The RCS uses a maximum width of the Z-search windowsbounded by the maximum round trip propagation delay.

The pre-track period immediately follows the acquisition orre-acquisition algorithms and immediately precedes the trackingalgorithm. Pre-track is a fixed duration period during which the receivedata provided by the modem is not considered valid. The pre-track periodallows other modem algorithms, such as those used by the SW PLL 1724,acquisition and tracking circuit 1701, AMF weight generator 1722, toprepare and adapt to the current channel. The pre-track period is twoparts. The first part is the delay while the code tracking loop pullsin. The second part is the delay while the AMF tap weight calculationsare performed by the AMF weight generator 1722 to produce settledweighting coefficients. Also in the second part of the pre-track period,the carrier tracking loop is allowed to pull in by the SW PLL 1724, andthe scalar quantile estimates are performed in the quantile estimationlogic 1723.

The tracking process is entered after the pre-track period ends. Thisprocess is actually a repetitive cycle and is the only process phaseduring which receive data provided by the modem may be considered valid.The following operations are performed during this phase: AMF tap weightupdate, carrier tracking, code tracking, vector quantile update, scalarquantile update, code lock check, derotation and symbol summing andpower control (forward and reverse)

If LOL is detected, the modem receiver terminates the track algorithmand automatically enters the reacquisition algorithm. In the SU, a LOLcauses the transmitter to be shut down. In the RCS, LOL causes forwardpower control to be disabled with the transmit power held constant atthe level immediately prior to loss of lock. It also causes the returnpower control information being transmitted to assume a “010101 . . . ”pattern, causing the SU to hold its transmit power constant. This can beperformed using the signal lock check function which generates the resetsignal to the acquisition and tracking circuit 1701.

Two sets of quantile statistics are maintained, one by quantileestimator 1733 and the other by the scalar quantile estimator 1723. Bothare used by the modem controller 1303. The first set is the “vector”quantile information, so named because it is calculated from the vectorof four complex values generated by the AUX AVC receiver 1712. Thesecond set is the scalar quantile information, which is calculated fromthe single complex value AUX signal that is output from the AUXdespreader 1707. The two sets of information represent different sets ofnoise statistics used to maintain a pre-determined probability of falsealarm (P_(fa)). The vector quantile data is used by the acquisition andreacquisition algorithms implemented by the modem controller 1303 todetermine the presence of a received signal in noise, and the scalarquantile information is used by the code lock check algorithm.

For both the vector and scalar cases, quantile information consists ofcalculated values of lambda0 through lambda2, which are boundary valuesused to estimate the probability distribution function (p.d.f.) of thedespread receive signal and determine whether the modem is locked to thePN code. The aux_power value used in the following C-subroutine is themagnitude squared of the AUX signal output of the scalar correlatorarray for the scalar quantiles, and the sum of the magnitudes squaredfor the vector case. In both cases the quantiles are then calculatedusing the following C-subroutine:

-   for (n=0; n<3; n++) {lambda [n]+=(lambda [n]<Aux_Power)? CG[n]:    GM[n]; }    where CG[n] are positive constants and GM[n] are negative constants,    (different values are used for scalar and vector quantiles).

During the acquisition phase, the search of the incoming pilot signalwith the locally generated pilot code sequence employs a series ofsequential tests to determine if the locally generated pilot code hasthe correct code phase relative to the received signal. The searchalgorithms use the sequential probability ratio test (SPRT) to determinewhether the received and locally generated code sequences are in phase.The speed of acquisition is increased by parallelism resulting fromhaving a multi-fingered receiver. For example, in the describedembodiment of the invention the main pilot rake 1711 has a total of 11fingers representing a total phase period of 11 chip periods. Foracquisition 8 separate SPRTs are implemented, with each SPRT observing a4 chip window. Each window is offset from the previous window by onechip, and in a search sequence any given code phase is covered by 4windows. If all 8 of the SPRT tests are rejected, then the set ofwindows is moved by 8 chips. If any of the SPRT's is accepted, then thecode phase of the locally generated pilot code sequence is adjusted toattempt to center the accepted SPRT's phase within the pilot AVC. It islikely that more than one SPRT reaches the acceptance threshold at thesame time. A table lookup is used to cover all 256 possible combinationsof accept/reject and the modem controller uses the information toestimate the correct center code phase within the pilot rake 1711. EachSPRT is implemented as follows (all operations occur at 64 k symbolrate): Denote the fingers' output level values as I_Finger[n] andQ_Finger[n], where n=0 . . . 10 (inclusive, 0 is earliest (mostadvanced) finger), then the power of each window is:${{Power}\quad{{Window}\quad\lbrack i\rbrack}} = {\sum\limits_{n = 0}^{10}\left( {{{I\_ Finger}^{2}\lbrack n\rbrack} + {{Q\_ Finger}^{2}\lbrack n\rbrack}} \right)}$

To implement the SPRT's the modem controller then performs for each ofthe windows the following calculations which are expressed as apseudo-code subroutine: /* find bin for Power */ tmp = SIGMA[0]; for (k= 0;k < 3; k++) {   if (Power > lambda [k]) tmp = SIGMA[k + 1]; }test_statistic += tmp; /* update statistic */ if(test_statistic >ACCEPTANCE_THRESHOLD)you've got ACQ; else if (test_statistic <DISMISSAL_THRESHOLD) {   forget this code phase; } else keep trying -get more statistics;where lambda[k] are as defined in the above section on quantileestimation, and SIGMA[k], ACCEPTANCE_THRESHOLD and DISMISSAL_THRESHOLDare predetermined constants. Note that SIGMA[k] is negative for lowvalues of k, and positive for right values of k, such that theacceptance and dismissal thresholds can be constants rather than afunction of how many symbols worth of data have been accumulated in thestatistic.

The modem controller determines which bin delimited by the values oflambda[k] the power level falls into which allows the modem controllerto develop an approximate statistic.

For the present algorithm, the control voltage is formed as ε=y^(T)By,where y is a vector formed from the complex valued output values of thepilot vector correlator 1711, and B is a matrix consisting of theconstant values pre-determined to maximize the operating characteristicswhile minimizing the noise as described previously with reference to thequadratic detector.

To understand the operation of the quadratic detector, it is useful toconsider the following. A spread spectrum (CDMA) signal, s(t) is passedthrough a multipath channel with an impulse response h_(c)(t). Thebaseband spread signal is described by Equation (30): $\begin{matrix}{{s(t)} = {\sum\limits_{i}{C_{i}{p\left( {t - {i\quad T_{c}}} \right)}}}} & {{Equation}\quad(30)}\end{matrix}$where C_(i) is a complex spreading code symbol, p(t) is a predefinedchip pulse and T_(c) is the chip time spacing, where T_(c)=1/R_(c) andR_(c) is the chip rate.

The received baseband signal is represented by Equation (31):$\begin{matrix}{{r(t)} = {{\sum\limits_{i}{C_{i}{q\left( {t - {i\quad T_{c}} - \tau} \right)}}} + {n(t)}}} & {{Equation}\quad(31)}\end{matrix}$where q(t)=p(t)*h_(c)(t), τ is an unknown delay and n(t) is additivenoise. The received signal is processed by a filter, h_(R)(t), so thewaveform, x(t), to be processed is given by Equation (32):$\begin{matrix}{{x(t)} = {{\sum\limits_{i}{C_{i}{f\left( {t - {iT}_{c} - \tau} \right)}}} + {z(t)}}} & {{Equation}\quad(32)}\end{matrix}$where f(t)=q(t)*h_(R)(t) and z(t)=n(t)*h_(R)(t).

In the exemplary receiver, samples of the received signal are taken atthe chip rate, that is to say, 1/T_(c). These samples, x(mT_(c)+τ′), areprocessed by an array of correlators that compute, during the r^(th)correlation period, the quantities given by Equation (33):$\begin{matrix}{v_{k}^{(r)} = {\sum\limits_{m = {rL}}^{{rL} + L - 1}{{x\left( {{mT}_{c} + \tau^{\prime}} \right)}C_{m + k}^{*}}}} & {{Equation}\quad(33)}\end{matrix}$These quantities are composed of a noise component w_(k) ^((r)) and adeterministic component y_(k) ^((r)) given by Equation (34):y _(k) ^((r)) =E└v _(k) ^((r)┘) =Lf(kT _(c)+τ′−τ)  Equation (34)In the sequel, the time index r may be suppressed for ease of writing,although it is to be noted that the function f(t) changes slowly withtime.

The samples are processed to adjust the sampling phase, τ′, in anoptimum fashion for further processing by the receiver, such as matchedfiltering. This adjustment is described below. To simplify therepresentation of the process, it is helpful to describe it in terms ofthe function f(t+τ), where the time-shift, τ, is to be adjusted. It isnoted that the function f(t+τ) is measured in the presence of noise.Thus, it may be problematical to adjust the phase τ′ based onmeasurements of the signal f(t+τ). To account for the noise, thefunction v(t): v(t)=f(t)+m(t) is introduced, where the term m(t)represents a noise process. The system processor may be derived based onconsiderations of the function v(t).

The process is non-coherent and therefore is based on the envelope powerfunction |v(t+τ)|². The functional e(τ′) given in Equation (35) ishelpful for describing the process:e(τ′)=∫_(−∞) ^(∞) |v(t+τ′−τ)|² dt−∫ ₀ ^(∞) |v(t+τ′τ)|² dt  Equation (35)The shift parameter is adjusted for e(τ′)=0, which occurs when theenergy on the interval (−∞, τ′−τ] equals that on the interval [τ′−τ, ∞).The error characteristic is monotonic and therefore has a single zerocrossing point. This is the desirable quality of the functional. Adisadvantage of the functional is that it is ill-defined because theintegrals are unbounded when noise is present. Nevertheless, thefunctional e(τ′) may be cast in the form given by Equation (36):e(τ′)=∫_(−∞) ⁰ w(t)|v(t+τ′−τ)|² dt  Equation (36)where the characteristic function w(t) is equal to sgn(t), the signumfunction.

To optimize the characteristic function w(t), it is helpful to define afigure of merit, F, as set forth in Equation (37): $\begin{matrix}{F = \frac{\overset{\_}{\left\lbrack {{e\left( {\tau_{0}^{\prime} + T_{A}} \right)} - {e\left( {\tau_{0}^{\prime} - T_{A}} \right)}} \right\rbrack^{2}}}{{VAR}\left\{ {e\left( \tau_{o}^{\prime} \right)} \right\}}} & {{Equation}\quad(37)}\end{matrix}$The numerator of F is the numerical slope of the mean errorcharacteristic on the interval [−T_(A),T_(A)] surrounding the trackedvalue, τ₀′. The statistical mean is taken with respect to the noise aswell as the random channel, h_(c)(t). It is desirable to specify astatistical characteristic of the channel in order to perform thisstatistical average. For example, the channel may be modeled as a widesense stationary uncorrelated scattering (WSSUS) channel with impulseresponse h_(c)(t) and a white noise process U(t) that has an intensityfunction g(t) as shown in Equation (38):h _(c)(t)={square root}{square root over (g(t))}U(t)  Equation (38)The variance of e(τ) is computed as the mean square value of thefluctuation:e′(r)=e(τ)−<e(r)>  Equation (39)where <e(τ)> is the average of e(τ) with respect to the noise.

Optimization of the figure of merit F with respect to the function w(t)may be carried out using well-known variational methods of optimization.Once the optimal w(t) is determined, the resulting processor may beapproximated accurately by a quadratic sample processor which is derivedas follows. By the sampling theorem, the signal v(t), bandlimited to abandwidth W may be expressed in terms of its samples as shown inEquation (40):v(t)=Σv(k/W)sinc[(Wt−k)π]  Equation (40)substituting this expansion into Equation (36) results in an infinitequadratic form in the samples v(k/W+τ′−Σ). Making the assumption thatthe signal bandwidth equals the chip rate allows the use of a samplingscheme that is clocked by the chip clock signal to be used to obtain thesamples. These samples, v_(k) are represented by Equation (41):v _(k) =v(kT _(c)+τ′−τ)  Equation (41)This assumption leads to a simplification of the implementation. It isvalid if the aliasing error is small.

In practice, the quadratic form that is derived is truncated. An examplenormalized B matrix is given below in Table 12. For this example, anexponential delay spread profile g(t)=exp(−t/τ) is assumed with τ equalto one chip. An aperture parameter T_(A) equal to one and one-half chipshas also been assumed. The underlying chip pulse has a raised cosinespectrum with a 20% excess bandwidth. TABLE 12 Example B Matrix 0 0 0 00 0 0 0 0 0 0 0 0 −0.1 0 0 0 0 0 0 0 0 0 −0.1 0.22 0.19 −0.19 0 0 0 0 00 0 0 0.19 1 0.45 −0.2 0 0 0 0 0 0 0 −0.19 0.45 0.99 0.23 0 0 0 0 0 0 00 −0.2 0.23 0 −0.18 0.17 0 0 0 0 0 0 0 0 −0.18 −0.87 −0.42 0.18 0 0 0 00 0 0 0.17 −0.42 −0.92 −0.16 0 0 0 0 0 0 0 0 0.18 −0.16 −0.31 0 0 0 0 00 0 0 0 0 0 −0.13 0 0 0 0 0 0 0 0 0 0 0 0Code tracking is implemented via a loop phase detector that isimplemented as follows. The vector y is defined as a column vector whichrepresents the 11 complex output level values of the pilot AVC 1711, andB denotes an 11×11 symmetric real valued coefficient matrix withpre-determined values to optimize performance with the non-coherentpilot AVC output values y. The output signal ε of the phase detector isgiven by Equation (42):ε=y ^(T) By  Equation (42)The following calculations are then performed to implement aproportional plus integral loop filter and the VCO:

-   x[n]=x[n−1]+βε-   z[n]=z[n−1]+x[n]+δε

for β and δ which are constants chosen from modeling the system tooptimize system performance for the particular transmission channel andapplication, and where x[n] is the loop filter's integrator output valueand z[n] is the VCO output value. The code phase adjustments are made bythe modem controller in the following C-subroutine: if (z > zmx) { delayphase 1/16 chip; z −= zmax; } else if (z < −zmax) { advance phase 1/16chip; z += zmax; }

A different delay phase could be used in the above pseudo-codeconsistant with the present invention.

The AMF tap-weight update algorithm of the AMF weight generator 1722occurs periodically to de-rotate and scale the phase of each fingervalue of the pilot rake 1711 by performing a complex multiplication ofthe pilot AVC finger value with the complex conjugate of the currentoutput value of the carrier tracking loop and applying the product to alow pass filter and form the complex conjugate of the filter values toproduce AMF tap-weight values, which are periodically written into theAMF filters of the CDMA modem.

The lock check algorithm, shown in FIG. 17, is implemented by the modemcontroller 1303 performing SPRT operations on the output signal of thescalar correlator array. The SPRT technique is the same as that for theacquisition algorithms, except that the acceptance and rejectionthresholds are changed to increase the probability of detection of lock.

Carrier tracking is accomplished via a second order loop that operateson the pilot output values of the scalar correlated array. The phasedetector output is the hard limited version of the quadrature componentof the product of the (complex valued) pilot output signal of the scalarcorrelated array and the VCO output signal. The loop filter is aproportional plus integral design. The VCO is a pure summation,accumulated phase error φ, which is converted to the complex phaser cosφ+j sin φ using a look-up table in memory.

The previous description of acquisition and tracking algorithm focuseson a non-coherent method because the acquisition and tracking algorithmdescribed requires non-coherent acquisition followed by non-coherenttracking because during acquisition a coherent reference is notavailable until the AMF, pilot AVC, aux AVC, and DPLL are in anequilibrium state. However, it is known in the art that coherenttracking and combining is always optimal because in non-coherenttracking and combining the output phase information of each pilot AVCfinger is lost. Consequently, another embodiment of the inventionemploys a two step acquisition and tracking system, in which thepreviously described non-coherent acquisition and tracking algorithm isimplemented first, and then the algorithm switches to a coherenttracking method. The coherent combining and tracking method is similarto that described previously, except that the error signal tracked is ofthe form:ε=y ^(T) Ay  Equation (43)where y is defined as a column vector which represents the 11 complexoutput level values of the pilot AVC 1711, and A denotes an 11×11symmetric real valued coefficient matrix with pre-determined values tooptimize performance with the coherent pilot AVC outputs y. An exemplaryA matrix is shown below. $\begin{matrix}{A = \begin{matrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & {- 1} & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1} & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1} & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1} & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & {- 1}\end{matrix}} & {{Equation}\quad(44)}\end{matrix}$

Referring to FIG. 9, the video distribution controller board (VDC) 940of the RCS is connected to each MIU 931, 932, 933 and the RFtransmitters/receivers 950. The VDC 940 is shown in FIG. 21. The datacombiner circuitry (DCC) 2150 includes a data demultiplexer 2101, datasummer 2102, FIR filters 2103, 2104 and a driver 2111. The DCC 2150: 1)receives the weighted CDMA modem I and Q data signal MDAT from each ofthe MIUs, 931, 932, 933, 2) sums the I and Q data with the digitalbearer channel data from each MIU 931, 932, 933, 3) and sums the resultwith the broadcast data message signal BCAST and the global pilotspreading code GPILOT provided by the master MIU modem 1210, 4) bandshapes the summed signals for transmission, and 5) produces analog datasignal for transmission to the RF transmitter/receiver.

FIR filters 2103, 2104 are used to modify the MIU CDMA transmit I and Qmodem data before transmission. The WAC transfers FIR filter coefficientdata through the serial port link 912 through the VDC controller 2120and to the FIR filters 2103, 2104. Each FIR filter 2103, 2104 isconfigured separately. The FIR Filters 2103, 2104 employ up-sampling tooperate at twice the chip rate so zero data values are sent after everyMIU CDMA transmit modem DATI and DATQ value to produce FTXI and FTXQ.

The VDC 940 distributes the AGC signal AGCDATA from the AGC 1750 of theMIUs 931, 932, 933 to the RF transmitter/receiver 950 through thedistribution interface (DI) 2110. The VDC DI 2110 receives data RXI andRXQ from the RF transmitter/receiver and distributes the signal asVDATAI and VDATAQ to MIUs 931, 932, 933.

Referring to FIG. 21, the VDC 940 also includes a VDC controller 2120which monitors status and fault information signals MIUSTAT from MIUsand connects to the serial link 912 and HSBS 970 to communicate with WAC920 shown in FIG. 9. The VDC controller 2120 includes a microprocessor,such as an Intel 8032 microcontroller, an oscillator (not shown)providing timing signals, and memory (not shown). The VDC controllermemory includes a flash PROM (not shown) to contain the controllerprogram code for the 8032 microprocessor, and an SRAM (not shown) tocontain the temporary data written to and read from memory by themicroprocessor.

Referring to FIG. 9, the present invention includes an RFtransmitter/receiver 950 and power amplifier section 960. Referring toFIG. 22, the RF transmitter/receiver 950 is divided into three sections:the transmitter module 2201, the receiver module 2202, and the frequencysynthesizer 2203. Frequency synthesizer 2203 produces a transmit carrierfrequency TFREQ and a receive carrier frequency RFREQ in response to afrequency control signal FREQCTRL received from the WAC 920 on theserial link 912. In the transmitter module 2201, the input analog I andQ data signals TXI and TXQ from the VDC are applied to the quadraturemodulator 2220, which also receives a transmit carrier frequency signalTFREQ from the frequency synthesizer 2203 to produce a quadraturemodulated transmit carrier signal TX. The analog transmit carriermodulated signal, an upconverted RF signal, TX is then applied to thetransmit power amplifier 2252 of the power amplifier 960. The amplifiedtransmit carrier signal is then passed through the high power passivecomponents (HPPC) 2253 to the Antenna 2250, which transmits theupconverted RF signal to the communication channel as a CDMA RF signal.In one embodiment of the invention, the transmit power amplifier 2252comprises eight amplifiers of approximately 60 watts peak-to-peak each.

The HPPC 2253 comprises a lightning protector, an output filter, a 10 dBdirectional coupler, an isolator, and a high power termination attachedto the isolator.

A receive CDMA RF signal is received at the antenna 2250 from the RFchannel and passed through the HPPC 2253 to the receive power amplifier2251. The receive power amplifier 2251 includes, for example, a 30 wattpower transistor driven by a 5 watt transistor. The RF receive module2202 has quadrature modulated receive carrier signal RX from the receivepower amplifier. The receive module 2202 includes a quadraturedemodulator 2210 which takes the receive carrier modulated signal RX andthe receive carrier frequency signal RFREQ from the frequencysynthesizer 2203, synchronously demodulates the carrier and providesanalog I and Q channels. These channels are filtered to produce thesignals RXI and RXQ, which are transferred to the VDC 940.

XXVI. The Subscriber Unit

FIG. 23 shows the subscriber unit (SU) of one embodiment of the presentinvention. As shown, the SU includes an RF section 2301 including an RFmodulator 2302, RF demodulator 2303 and splitter/isolator 2304 whichreceive global and assigned logical channels including traffic andcontrol messages and global pilot signals in the forward link CDMA RFchannel signal, and transmit assigned channels and reverse pilot signalsin the reverse link CDMA RF channel. The forward and reverse links arereceived and transmitted respectively through antenna 2305. The RFsection employs, in one exemplary embodiment, a conventional dualconversion superheterodyne receiver having a synchronous demodulatorresponsive to the signal ROSC. Selectivity of such a receiver isprovided by a 70 MHz transversal SAW filter (not shown). The RFmodulator includes a synchronous modulator (not shown) responsive to thecarrier signal TOSC to produce a quadrature modulated carrier signal.This signal is stepped up in frequency by an offset mixing circuit (notshown).

The SU further includes a subscriber line interface 2310, including thefunctionality of a control (CC) generator, a data interface 2320, anADPCM encoder 2321, an ADPCM decoder 2322, an SU controller 2330, an SUclock signal generator 2331, memory 2332 and a CDMA modem 2340, which isessentially the same as the CDMA modem 1210 described above withreference to FIG. 13. It is noted that data interface 2320, ADPCMencoder 2321 and ADPCM decoder 2322 are typically provided as a standardADPCM encoder/decoder chip.

The forward link CDMA RF channel signal is applied to the RF demodulator2303 to produce the forward link CDMA signal. The forward link CDMAsignal is provided to the CDMA modem 2340, which acquiressynchronization with the global pilot signal, produces global pilotsynchronization signal to the clock 2331, to generate the system timingsignals, and despreads the plurality of logical channels. The CDMA modem2340 also acquires the traffic messages RMESS and control messages RCTRLand provides the traffic message signals RMESS to the data interface2320 and receive control message signals RCTRL to the SU controller2330.

The receive control message signals RCTRL include a subscriberidentification signal, a coding signal and bearer modification signals.The RCTRL may also include control and other telecommunication signalinginformation. The receive control message signal RCTRL is applied to theSU controller 2330, which verifies that the call is for the SU from thesubscriber identification value derived from RCTRL. The SU controller2330 determines the type of user information contained in the trafficmessage signal from the coding signal and bearer rate modificationsignal. If the coding signal indicates the traffic message is ADPCMcoded, the traffic message RVMESS is sent to the ADPCM decoder 2322 bysending a select message to the data interface 2320. The SU controller2330 outputs an ADPCM coding signal and bearer rate signal derived fromthe coding signal to the ADPCM decoder 2322. The traffic message signalRVMESS is the input signal to the ADPCM decoder 2322, where the trafficmessage signal is converted to a digital information signal RINF inresponse to the values of the input ADPCM coding signal.

If the SU controller 2330 determines the type of user informationcontained in the traffic message signal from the coding signal is notADPCM coded, then RDMESS passes through the ADPCM encoder transparently.The traffic message RDMESS is transferred from the data interface 2320directly to the interface controller (IC) 2312 of the subscriber lineinterface 2310.

The digital information signal RINF or RDMESS is applied to thesubscriber line interface 2310, including an interface controller (IC)2312 and line interface (LI) 2313. For the exemplary embodiment the ICis an extended PCM interface controller (EPIC) and the LI is asubscriber line interface circuit (SLIC) for POTS which corresponds toRINF type signals and an ISDN Interface for ISDN which corresponds toRDMESS type signals. The EPIC and SLIC circuits are well known in theart. The subscriber line interface 2310 converts the digital informationsignal RINF or RDMESS to the user defined format. The user definedformat is provided to the IC 2312 from the SU Controller 2330. The LI2310 includes circuits for performing such functions as A-law or μ-lawconversion, generating dial tone and generating or interpretingsignaling bits. The line interface also produces the user informationsignal to the SU user 2350 as defined by the subscriber line interface,for example POTS voice, voiceband data or ISDN data service.

For a reverse link CDMA RF channel, a user information signal is appliedto the LI 2313 of the subscriber line interface 2310, which outputs aservice type signal and an information type signal to the SU controller.The IC 2312 of the subscriber line interface 2310 produces a digitalinformation signal TINF which is the input signal to the ADPCM encoder2321 if the user information signal is to be ADPCM encoded, such as forPOTS service. For data or other non-ADPCM encoded user information, theIC 2312 passes the data message TDMESS directly to the data interface2320. The call control module (CC), including the subscriber lineinterface 2310, derives call control information from the userinformation signal, and passes the call control information CCINF to theSU controller 2330. The ADPCM encoder 2321 also receives coding signaland bearer modification signals from the SU controller 2330 and convertsthe input digital information signal into the output message trafficsignal TVMESS in response to the coding and bearer modification signals.The SU controller 2330 also outputs the reverse control signal whichincludes the coding signal call control information, and bearer channelmodification signal, to the CDMA modem. The output message signal TVMESSis applied to the data interface 2320. The data interface 2320 sends theuser information to the CDMA modem 2340 as transmit message signalTMESS. The CDMA modem 2340 spreads the output message and reversecontrol channels TCTRL received from the SU controller 2330 and producesthe reverse link CDMA signal. The reverse link CDMA signal is providedto the RF transmit section 2301 and modulated by the RF modulator 2302to produce the output reverse link CDMA RF channel signal transmittedfrom antenna 2305.

XXVII. Call Connection and Establishment Procedure

The process of bearer channel establishment consists of two procedures:the call connection process for a call connection incoming from a remotecall processing unit such as an RDU (incoming call connection), and thecall connection process for a call outgoing from the SU (outgoing callconnection). Before any bearer channel can be established between an RCSand an SU, the SU must register its presence in the network with theremote call processor such as the RDU. When the off-hook signal isdetected by the SU, the SU not only begins to establish a bearerchannel, but also initiates the procedure for an RCS to obtain aterrestrial link between the RCS and the remote processor. Asincorporated herein by reference, the process of establishing the RCSand RDU connection is detailed in the DECT V5.1 standard.

For the incoming call connection procedure shown in FIG. 24, first 2401,the WAC 920 (shown in FIG. 9) receives, via one of the MUXs 905, 906 and907, an incoming call request from a remote call processing unit. Thisrequest identifies the target SU and that a call connection to the SU isdesired. The WAC periodically outputs the SBCH channel with pagingindicators for each SU and periodically outputs the FBCH traffic lightsfor each access channel. In response to the incoming call request, theWAC, at step 2420, first checks to see if the identified SU is alreadyactive with another call. If so, the WAC returns a busy signal for theSU to the remote processing unit through the MUX, otherwise the pagingindicator for the channel is set.

Next, at step 2402, the WAC checks the status of the RCS modems and, atstep 2421, determines whether there is an available modem for the call.If a modem is available, the traffic lights on the FBCH indicate thatone or more AXCH channels are available. If no channel is availableafter a certain period of time, then the WAC returns a busy signal forthe SU to the remote processing unit through the MUX. If an RCS modem isavailable and the SU is not active (in sleep mode), the WAC sets thepaging indicator for the identified SU on the SBCH to indicate anincoming call request. Meanwhile, the access channel modems continuouslysearch for the short access pilot signal (SAXPT) of the SU.

At step 2403, an SU in sleep mode periodically enters awake mode. Inawake mode, the SU modem synchronizes to the downlink pilot signal,waits for the SU modem AMF filters and phase locked loop to settle, andreads the paging indicator in the slot assigned to it on the SBCH todetermine if there is a call for the SU 2422. If no paging indicator isset, the SU halts the SU modem and returns to sleep mode. If a pagingindicator is set for an incoming call connection, the SU modem checksthe service type and traffic lights on FBCH for an available AXCH.

Next, at step 2404, the SU modem selects an available AXCH and starts afast transmit power ramp-up on the corresponding SAXPT. For a period theSU modem continues fast power ramp-up on SAXPT and the access modemscontinue to search for the SAXPT.

At step 2405, the RCS modem acquires the SAXPT of the SU and begins tosearch for the SU LAXPT. When the SAXPT is acquired, the modem informsthe WAC controller, and the WAC controller sets the traffic lightscorresponding to the modem to “red” to indicate the modem is now busy.The traffic lights are periodically output while continuing to attemptacquisition of the LAXPT.

The SU modem monitors, at step 2406, the FBCH AXCH traffic light. Whenthe AXCH traffic light is set to red, the SU assumes the RCS modem hasacquired the SAXPT and begins transmitting LAXPT. The SU modem continuesto ramp-up power of the LAXPT at a slower rate until sync-ind messagesare received on the corresponding CTCH. If the SU is mistaken becausethe traffic light was actually set in response to another SU acquiringthe AXCH, the SU modem times out because no sync-ind messages arereceived. The SU randomly waits a period of time, picks a new AXCHchannel, and steps 2404 and 2405 are repeated until the SU modemreceives sync-ind messages. Details of the power ramp-up method used inthe exemplary embodiment of this invention are described in U.S. Pat.No. 5,841,768 entitled “Method Of Controlling Initial Power Ramp-Up InCDMA Systems By Using Short Codes” by Ozluturk et al. which isincorporated herein by reference.

Next, at step 2407, the RCS modem acquires the LAXPT of the SU andbegins sending sync-ind messages on the corresponding CTCH. The modemwaits 10 msec for the pilot and AUX Vector correlator filters andphase-locked loop to settle, but continues to send sync-ind messages onthe CTCH. The modem then begins looking for a request message for accessto a bearer channel (MAC_ACC_REQ), from the SU modem.

The SU modem, at step 2408, receives the sync-ind message and freezesthe LAXPT transmit power level. The SU modem then begins sendingrepeated request messages for access to a bearer traffic channel(MAC_ACC_REQ) at fixed power levels, and listens for a requestconfirmation message (MAC_BEARER_CFM) from the RCS modem.

Next, at step 2409, the RCS modem receives a MAC_ACC_REQ message; themodem then starts measuring the AXCH power level, and starts the APCchannel. The RCS modem then sends the MAC_BEARER_CFM message to the SUand begins listening for the acknowledgment MAC_BEARER_CFM_ACK of theMAC_BEARER_CFM message. At step 2410, the SU modem receives theMAC_BEARER_CFM message and begins obeying the APC power controlmessages. The SU stops sending the MAC_ACC_REQ message and sends the RCSmodem the MAC_BEARER_CFM_ACK message. The SU begins sending the nulldata on the AXCH. The SU waits 10 msec for the uplink transmit powerlevel to settle.

The RCS modem, at step 2411, receives the MAC_BEARER_CFM_ACK message andstops sending the MAC_BEARER_CFM messages. APC power measurementscontinue.

Next, at step 2412, both the SU and the RCS modems have synchronized thesub-epochs, obey APC messages, measure receive power levels, and computeand send APC messages. The SU waits 10 msec for downlink power level tosettle.

Finally, at step 2413, the bearer channel is established and initializedbetween the SU and RCS modems. The WAC receives the bearer establishmentsignal from the RCS modem, re-allocates the AXCH channel and sets thecorresponding traffic light to green.

For the Outgoing Call Connection shown in FIG. 25, the SU is placed inactive mode by the off-hook signal at the user interface at step 2501.

Next, at step 2502, the RCS indicates available AXCH channels by settingthe respective traffic lights.

At step 2503, the SU synchronizes to the downlink pilot, waits for theSU modem vector correlator filters and phase lock loop to settle, andthe SU checks service type and traffic lights for an available AXCH.Steps 2504 through 2513 are identical to the procedure steps 2404through 2413 for the incoming call connection procedure of FIG. 24, andtherefore are not explained in detail.

In the previous procedures for incoming call connection and outgoingcall connection, the power ramping-up process consists of the followingevents. The SU starts from very low transmit power and increases itspower level while transmitting the short code SAXPT; once the RCS modemdetects the short code it turns off the traffic light. Upon detectingthe changed traffic light, the SU continues ramping-up at a slower ratethis time sending the LAXPT. Once the RCS modem acquires the LAXPT andsends a message on CTCH to indicate this, the SU keeps its transmit (TX)power constant and sends the MAC-access-request message. This message isanswered with a MAC_BEARER_CFM message on the CTCH. Once the SU receivesthe MAC_BEARER_CFM message it switches to the traffic channel (TRCH)which is the dial tone for POTS.

When the SU captures a specific user channel AXCH, the RCS assigns acode seed for the SU through the CTCH. The code seed is used by thespreading code generator in the SU modem to produce the assigned codefor the reverse pilot of the SU, and the spreading codes for associatedchannels for traffic, call control, and signaling. The SU reverse pilotspreading code sequence is synchronized in phase to the RCS systemglobal pilot spreading code sequence, and the traffic, call control andsignaling spreading codes are synchronized in phase to the SU reversepilot spreading code sequence.

If the SU is successful in capturing a specific user channel, the RCSestablishes a terrestrial link with the remote processing unit tocorrespond to the specific user channel. For the DECT V5.1 standard,once the complete link from the RDU to the LE is established using theV5.1 ESTABLISHMENT message, a corresponding V5.1 ESTABLISHMENT ACKmessage is returned from the LE to the RDU, and the SU is sent a CONNECTmessage indicating that the transmission link is complete.

XXVIII. Support of Special Service Types

The system of the present invention includes a bearer channelmodification feature which allows the transmission rate of the userinformation to be switched from a lower rate to a higher rate. Thebearer channel modification (BCM) method is used to change a 32 kb/sADPCM channel to a 64 kb/s PCM channel to support high speed data andfax communications through the spread-spectrum communication system ofthe present invention. Although the details of this technique aredescribed in U.S. Pat. No. 5,953,346 entitled “CDMA Communication SystemWhich Selectively Suppresses Data Transmissions During Establishment ofa Communication Channel” by Michael J. Luddy, the process is brieflydescribed below:

First, a bearer channel on the RF interface is established between theRCS and SU, and a corresponding link exists between the RCS terrestrialinterface and the remote processing unit, such as an RDU. The digitaltransmission rate of the link between the RCS and remote processing unitnormally corresponds to a data encoded rate, which may be, for example,ADPCM at 32 kb/s. The WAC controller of the RCS monitors the encodeddigital data information of the link received by the line interface ofthe MUX. If the WAC controller detects the presence of the 2100 Hz tonein the digital data, the WAC instructs the SU through the assignedlogical control channel and causes a second, 64 kb/s duplex link to beestablished between the RCS modem and the SU. In addition, the WACcontroller instructs the remote processing unit to establish a second 64kb/s duplex link between the remote processing unit and the RCS.Consequently, for a brief period, the remote processing unit and the SUexchange the same data over both the 32 kb/s and the 64 kb/s linksthrough the RCS. Once the second link is established, the remoteprocessing unit causes the WAC controller to switch transmission only tothe 64 kb/s link, and the WAC controller instructs the RCS modem and theSU to terminate and tear down the 32 kb/s link. Concurrently, the 32kb/s terrestrial link is also terminated and torn down.

Another embodiment of the BCM method incorporates a negotiation betweenthe external remote processing unit, such as the RDU, and the RCS toallow for redundant channels on the terrestrial interface, while onlyusing one bearer channel on the RF interface. The method described is asynchronous switchover from the 32 kb/s link to the 64 kb/s link overthe air link which takes advantage of the fact that the spreading codesequence timing is synchronized between the RCS modem and SU. When theWAC controller detects the presence of the 2100 Hz tone in the digitaldata, the WAC controller instructs the remote processing unit toestablish a second 64 kb/s duplex link between the remote processingunit and the RCS. The remote processing unit then sends 32 kb/s encodeddata and 64 kb/s data concurrently to the RCS. Once the remoteprocessing unit has established the 64 kb/s link, the RCS is informedand the 32 kb/s link is terminated and torn down. The RCS also informsthe SU that the 32 kb/s link is being torn down and to switch processingto receive unencoded 64 kb/s data on the channel. The SU and RCSexchange control messages over the bearer control channel of theassigned channel group to identify and determine the particular subepochof the bearer channel spreading code sequence within which the RCS willbegin transmitting 64 kbit/sec data to the SU. Once the subepoch isidentified, the switch occurs synchronously at the identified subepochboundary. This synchronous switchover method is more economical ofbandwidth since the system does not need to maintain capacity for a 64kb/s link in order to support a switchover.

In previously described embodiments of the BCM feature, the RCS willtear down the 32 kb/s link first, but one skilled in the art would knowthat the RCS could tear down the 32 kb/s link after the bearer channelhas switched to the 64 kb/s link.

As another special service type, the system of the present inventionincludes a method for conserving capacity over the RF interface for ISDNtypes of traffic. This conservation occurs while a known idle bitpattern is transmitted in the ISDN D-channel when no data information isbeing transmitted. The CDMA system of the present invention includes amethod to prevent transmission of redundant information carried on theD-channel of ISDN networks for signals transmitted through a wirelesscommunication link. The advantage of such method is that it reduces theamount of information transmitted and consequently the transmit powerand channel capacity used by that information. The method is describedas it is used in the RCS. In the first step, the controller, such as theWAC of the RCS or the SU controller of the SU, monitors the outputD-channel from the subscriber line interface for a pre-determinedchannel idle pattern. A delay is included between the output of the lineinterface and the CDMA modem. Once the idle pattern is detected, thecontroller inhibits the transmission of the spread message channelthrough a message included in the control signal to the CDMA modem. Thecontroller continues to monitor the output D-channel of the lineinterface until the presence of data information is detected. When datainformation is detected, the spread message channel is activated.Because the message channel is synchronized to the associated pilotwhich is not inhibited, the corresponding CDMA modem of the other end ofthe communication link does not have to reacquire synchronization to themessage channel.

XXIX. Drop Out Recovery

The RCS and SU each monitor the CDMA bearer channel signal to evaluatethe quality of the CDMA bearer channel connection. Link quality isevaluated using the SPRT process employing adaptive quantile estimation.The SPRT process uses measurements of the received signal power and, ifthe SPRT process detects that the local spreading code generator haslost synchronization with the received signal spreading code or if itdetects the absence or low level of a received signal, the SPRT declaresLOL.

When the LOL condition is declared, the receiver modem of each RCS andSU begins a Z-search of the input signal with the local spreading codegenerator. Z-search is well known in the art of CDMA spreading codeacquisition and detection and is described in Digital Communications andSpread Spectrum Systems, by Robert E. Ziemer and Roger L. Peterson, atpages 492-94 which is incorporated herein by reference. The Z-searchalgorithm of the present invention tests groups of eight spreading codephases ahead and behind the last known phase in larger and largerspreading code phase increments.

During the LOL condition detected by the RCS, the RCS continues totransmit to the SU on the assigned channels, and continues to transmitpower control signals to the SU to maintain SU transmit power level. Themethod of transmitting power control signals is described below.Successful reacquisition desirably takes place within a specified periodof time. If reacquisition is successful, the call connection continues,otherwise the RCS tears down the call connection by deactivating anddeallocating the RCS modem assigned by the WAC, and transmits a calltermination signal to a remote call processor, such as the RDU, asdescribed previously.

When the LOL condition is detected by the SU, the SU stops transmissionto the RCS on the assigned channels which forces the RCS into a LOLcondition, and starts the reacquisition algorithm. If reacquisition issuccessful, the call connection continues, and if not successful, theRCS tears down the call connection by deactivating and deallocating theSU modem as described previously.

XXX. Power Control

The power control feature of the present invention is used to minimizethe amount of transmit power used by an RCS and the SUs of the system,and the power control subfeature that updates transmit power duringbearer channel connection is defined as APC. APC data is transferredfrom the RCS to an SU on the forward APC channel and from an SU to theRCS on the reverse APC channel. When there is no active data linkbetween the two, the maintenance power control (MPC) subfeature updatesthe SU transmit power.

Transmit power levels of forward and reverse assigned channels andreverse global channels are controlled by the APC algorithm to maintainsufficient signal power to interference noise power ratio (SIR) on thosechannels, and to stabilize and minimize system output power. The presentinvention uses a closed loop power control mechanism in which a receiverdecides that the transmitter should incrementally raise or lower itstransmit power. This decision is conveyed back to the respectivetransmitter via the power control signal on the APC channel. Thereceiver makes the decision to increase or decrease the transmitter'spower based on two error signals. One error signal is an indication ofthe difference between the measured and desired despread signal powers,and the other error signal is an indication of the average receivedtotal power.

As used in the described embodiment of the invention, the term near-endpower control is used to refer to adjusting the transmitter's outputpower in accordance with the APC signal received on the APC channel fromthe other end. This means the reverse power control for the SU andforward power control for the RCS; and the term far-end APC is used torefer to forward power control for the SU and reverse power control forthe RCS (adjusting the opposite end's transmit power).

In order to conserve power, the SU modem terminates a transmission andpowers-down while waiting for a call, defined as the sleep phase. Sleepphase is terminated by an awaken signal from the SU controller. The SUmodem acquisition circuit automatically enters the reacquisition phaseand begins the process of acquiring the downlink pilot, as describedpreviously.

XXXI. Closed Loop Power Control Algorithms

The near-end power control consists of two steps: first, the initialtransmit power is set; and second, the transmit power is continuallyadjusted according to information received from the far-end using APC.

For the SU, initial transmit power is set to a minimum value and thenramped up, for example, at a rate of 1 dB/ms until either a ramp-uptimer expires (not shown) or the RCS changes the corresponding trafficlight value on the FBCH to “red” indicating that the RCS has locked tothe SU's short pilot SAXPT. Expiration of the timer causes the SAXPTtransmission to be shut down, unless the traffic light value is set tored first, in which case the SU continues to ramp-up transmit power butat a much lower rate than before the “red” signal was detected.

For the RCS, initial transmit power is set at a fixed value,corresponding to the minimum value necessary for reliable operation asdetermined experimentally for the service type and the current number ofsystem users. Global channels, such as global pilot or, FBCH, are alwaystransmitted at the fixed initial power, whereas traffic channels areswitched to APC.

The APC bits are transmitted as one bit up or down signals on the APCchannel. In the described embodiment, the 64 kb/s APC data stream is notencoded or interleaved. Far-end power control consists of the near-endtransmitting power control information for the far-end to use inadjusting its transmit power. The APC algorithm causes the RCS or the SUto transmit +1 if the following inequality holds, otherwise −1.α₁ e ₁−α₂ e ₂>0  Equation (45)Here, the error signal e₁ is calculated as:e ₁ =P _(d)−(1+SNR _(REQ))P _(N)  Equation (46)where P_(d) is the despread signal plus noise power, P_(N) is thedespread noise power, and SNR_(REQ) is the desired despread signal tonoise ratio for the particular service type; and:e ₂ =P _(r) −P _(o)  Equation (47)where P_(r) is a measure of the received power and P_(o) is the AGCcircuit set point. The weights α₁ and α₂ in Equation (45) are chosen foreach service type and APC update rate.

XXXII. Maintenance Power Control

During the sleep phase of the SU, the interference noise power of theCDMA RF channel may change. The present invention includes a maintenancepower control feature (MPC) which periodically adjusts the SU's initialtransmit power with respect to the interference noise power of the CDMAchannel. The MPC is the process whereby the transmit power level of anSU is maintained within close proximity of the minimum level for the RCSto detect the SU's signal. The MPC process compensates for low frequencychanges in the required SU transmit power.

The maintenance control feature uses two global channels: one is calledthe status channel (STCH) on reverse link, and the other is called thecheck-up channel (CUCH) on forward link. The signals transmitted onthese channels carry no data and they are generated the same way theshort codes used in initial power ramp-up are generated. The STCH andCUCH codes are generated from a “reserved” branch of the global codegenerator.

The MPC process is as follows. At random intervals, the SU sends asymbol length spreading code periodically for 3 ms on the status channel(STCH). If the RCS detects the sequence, it replies by sending a symbollength code sequence within the next 3 ms on the check-up channel(CUCH). When the SU detects the response from the RCS, it reduces itstransmit power by a particular step size. If the SU does not see anyresponse from the RCS within that 3 ms period, it increases its transmitpower by the step size. Using this method, the RCS response istransmitted at a power level that is enough to maintain a 0.99 detectionprobability at all SU's.

The rate of change of traffic load and the number of active users isrelated to the total interference noise power of the CDMA channel. Theupdate rate and step size of the maintenance power update signal for thepresent invention is determined by using queuing theory methods wellknown in the art of communication theory, such as outlined in“Fundamentals of Digital Switching” (Plenum-New York) edited by McDonaldand incorporated herein by reference. By modeling the call originationprocess as an exponential random variable with mean 6.0 mins, numericalcomputation shows the maintenance power level of a SU should be updatedonce every 10 seconds or less to be able to follow the changes ininterference level using 0.5 dB step size. Modeling the call originationprocess as a Poisson random variable with exponential interarrivaltimes, arrival rate of 2×10⁻⁴ per second per user, service rate of 1/360per second, and the total subscriber population is 600 in the RCSservice area also yields by numerical computation that an update rate ofonce every 10 seconds is sufficient when 0.5 dB step size is used.

Maintenance power adjustment is performed periodically by the SU whichchanges from sleep phase to awake phase and performs the MPC process.Consequently, the process for the MPC feature is shown in FIG. 26 and isas follows: First, at step 2601, signals are exchanged between the SUand the RCS maintaining a transmit power level that is close to therequired level for detection: the SU periodically sends a symbol lengthspreading code in the STCH and the RCS periodically sends a symbollength spreading code in the CUCH as response.

Next, at step 2602, if the SU receives a response within 3 ms after theSTCH message it sent, it decreases its transmit power by a particularstep size at step 2603; but if the SU does not receive a response within3 ms after the STCH message, it increases its transmit power by the samestep size at step 2604.

The SU waits, at step 2605, for a period of time before sending anotherSTCH message, this time period is determined by a random process whichaverages 10 seconds.

Thus, the transmit power of the STCH messages from the SU is adjustedbased on the RCS response periodically, and the transmit power of theCUCH messages from the RCS is fixed (step 2606).

XXXIII. Mapping of Power Control Signal to Logical Channels For APC

Power control signals are mapped to specified logical channels forcontrolling transmit power levels of forward and reverse assignedchannels. Reverse global channels are also controlled by the APCalgorithm to maintain sufficient signal power to interference noisepower ratio (SIR) on those reverse channels, and to stabilize andminimize system output power. The present invention uses a closed looppower control method in which a receiver periodically decides toincrementally raise or lower the output power of the transmitter at theother end. The method also conveys that decision back to the respectivetransmitter. TABLE 13 APC Signal Channel Assignments Link ChannelsCall/Connection Power Control Method and Signals Status Initial ValueContinuous Reverse link being established as determined by APC bits inforward AXCH power ramping APC channel AXPT Reverse link in-progresslevel established APC bits in forward APC, OW, during call set-up APCchannel TRCH, pilot signal Forward link in-progress fixed value APC bitsin reverse APC, OW, APC channel TRCH

Forward and reverse links are independently controlled. For acall/connection in process, forward link (TRCHs, APC, and OW) power iscontrolled by the APC bits transmitted on the reverse APC channel.During the call/connection establishment process, reverse link (AXCH)power is also controlled by the APC bits transmitted on the forward APCchannel. Table 13 summarizes the specific power control methods for thecontrolled channels.

The required SIRs of the assigned channels TRCH, APC and OW and reverseassigned pilot signal for any particular SU are fixed in proportion toeach other and these channels are subject to nearly identical fading,therefore, they are power controlled together.

XXXIV. AFPC

The AFPC process attempts to maintain the minimum required SIR on theforward channels during a call/connection. The AFPC recursive process,shown in FIG. 27, consists of the steps of having an SU form the twoerror signals e₁ and e₂ in step 2701 where:e ₁ =P _(d)−(1+SNR _(REQ))P _(N)  Equation (48)e ₂ =P _(r) −P _(o)  Equation (49)and P_(d) is the despread signal plus noise power, P_(N) is the despreadnoise power, SNR_(REQ) is the required signal to noise ratio for theservice type, P_(r) is a measure of the total received power, and P_(o)is the AGC set point. Next, the SU modem forms the combined error signalα₁e₁+α₂e₂ in step 2702. Here, the weights α₁ and α₂ are chosen for eachservice type and APC update rate. In step 2703, the SU hard limits thecombined error signal and forms a single APC bit. The SU transmits theAPC bit to the RCS in step 2704 and RCS modem receives the bit in step2705. The RCS increases or decreases its transmit power to the SU instep 2706 and the algorithm repeats starting from step 2701.

XXXV. ARPC

The ARPC process maintains the minimum desired SIR on the reversechannels to minimize the total system reverse output power, during bothcall/connection establishment and while the call/connection is inprogress. The recursive ARPC process, shown in FIG. 28, begins at step2801 where the RCS modem forms the two error signals e₁ and e₂ in step2801 where:e ₁ =P _(d)−(1+SNR _(REQ))P _(N)  Equation (50)e ₂ =P _(rt) −P _(o)  Equation (51)

and P_(d) is the despread signal plus noise power, P_(N) is the despreadnoise power, SNR_(REQ) is the desired signal to noise ratio for theservice type, P_(rt) is a measure of the average total power received bythe RCS, and P_(o) is the AGC set point. The RCS modem forms thecombined error signal α₁e₁+a₂e₂ in step 2802 and hard limits this errorsignal to determine a single APC bit in step 2803. The RCS transmits theAPC bit to the SU in step 2804, and the bit is received by the SU instep 2805. Finally, the SU adjusts its transmit power according to thereceived APC bit in step 2806, and the algorithm repeats starting fromstep 2801. TABLE 14 Symbols/Thresholds Used for APC Computation Serviceor Call/Connection Symbol (and Threshold) Call Type Status Used for APCDecision Don't care being established AXCH ISDN D SU in-progress one1/64-kb/s symbol from TRCH (ISDN-D) ISDN 1B + D SU in-progress TRCH(ISDN-B) ISDN 2B + D SU in-progress TRCH (one ISDN-B) POTS SUin-progress one 1/64-KBPS symbol from (64 KBPS PCM) TRCH, use 64 KBPSPCM threshold POTS SU in-progress one 1/64-KBPS symbol from (32 KBPSADPCM) TRON, use 32 KBPS ADPCM threshold Silent Maintenance in-progressOW (continuous during Call (any SU) a maintenance call)

XXXVI. SIR and Multiple Channel Types

The required SIR for channels on a link is a function of channel format(e.g. TRCH, OW), service type (e.g. ISDN B, 32 KBPS ADPCM POTS), and thenumber of symbols over which data bits are distributed (e.g. two 64 kb/ssymbols are integrated to form a single 32 kb/s ADPCM POTS symbol).Despreader output power corresponding to the required SIR for eachchannel and service type is predetermined. While a call/connection is inprogress, several user CDMA logical channels are concurrently active;each of these channels transfers a symbol every symbol period. The SIRof the symbol from the nominally highest SIR channel is measured,compared to a threshold and used to determine the APC step up/downdecision each symbol period. Table 14 indicates the symbol (andthreshold) used for the APC computation by service and call type.

XXXVII. APC Parameters

APC information is always conveyed as a single bit of information, andthe APC data rate is equivalent to the APC update rate. The APC updaterate is 64 kb/s. This rate is high enough to accommodate expectedRayleigh and Doppler fades and allow for a relatively high (˜0.2) biterror rate (BER) in the uplink and downlink APC channels, whichminimizes capacity devoted to the APC.

The power step up/down indicated by an APC bit is nominally between 0.1and 0.01 dB. The dynamic range for power control is 70 dB on the reverselink and 12 dB on the forward link for the exemplary embodiment of thepresent system.

XXXVIII. An Alternative Embodiment of Multiplexing of APC Information

The dedicated APC and OW logical channels described previously can alsobe multiplexed together in one logical channel. The APC information istransmitted at 64 kb/s continuously whereas the OW information occurs indata bursts. The alternative multiplexed logical channel includes theunencoded, non-interleaved 64 kb/s. APC information on, for example, thein-phase channel and the OW information on the quadrature channel of theQPSK signal.

XXXIX. Closed Loop Power Control Implementation

The closed loop power control during a call connection responds to twodifferent variations in overall system power. First, the system respondsto local behavior such as changes in power level of an SU, and second,the system responds to changes in the power level of the entire group ofactive users in the system.

The APS system of the exemplary embodiment of the present invention isshown in FIGS. 29A and 29B. As shown, the circuitry used to adjust thetransmitted power is similar for the RCS (shown as the RCS power controlmodule 2901) and SU (shown as the SU power control module 2902).Beginning with the RCS power control module 2901, the reverse link RFchannel signal is received at the RF antenna and demodulated to producethe reverse CDMA signal RMCH. The signal RMCH is applied to the variablegain amplifier (VGA1) 2910 which produces an input signal to the AGCcircuit 2911. The AGC 2911 produces a variable gain amplifier controlsignal into the VGA1 2910. This signal maintains the level of the outputsignal of VGA1 2910 at a near constant value. The output signal of VGA1is despread by the despread-demultiplexer (demux) 2912, which produces adespread user message signal MS and a forward APC bit. The forward APCbit is applied to the integrator 2913 to produce the forward APC controlsignal. The forward APC control signal controls the forward link VGA22914 and maintains the forward link RF channel signal at a minimumdesired level for communication.

The signal power of the despread user message signal MS of the RCS powermodule 2901 is measured by the power measurement circuit 2915 to producea signal power indication. The output of the VGA1 is also despread bythe AUX despreader 2981 which despreads the signal by using anuncorrelated spreading code, and hence obtains a despread noise signal.The power measurement by measure power 2982 of this signal is multipliedat multiplier 2983 by 1 plus the desired signal to noise ratio (SNR_(R))to form the threshold signal S1. The difference between the despreadsignal power and the threshold value S1 is produced by the subtracter2916. This difference is the error signal ES1, which is an error signalrelating to the particular SU transmit power level.

Similarly, the control signal for the VGA1 2910 is applied to the ratescaling circuit 2917 to reduce the rate of the control signal for VGA12910. The output signal of scaling circuit 2917 is a scaled system powerlevel signal SP1. The threshold compute logic 2918 calculates the systemsignal threshold value SST from the RCS user channel power data signalRCSUSR. The complement of the scaled system power level signal, SP1, andthe system signal power threshold value SST are applied to the adder2919 which produces the second error signal ES2. This error signal isrelated to the system transmit power level of all active SUs. The inputerror signals ES1 and ES2 are combined in the combiner 2920 to produce acombined error signal input to the delta modulator (DM1) 2921, and theoutput signal of the DM1 is the reverse APC bit stream signal, havingbits of value +1 or −1, which for the present invention is transmittedas a 64 kb/s signal.

The reverse APC bit is applied to the spreading circuit 2922, and theoutput signal of the spreading circuit 2922 is the spread-spectrumforward APC message signal. Forward OW and traffic signals are alsoprovided to spreading circuits 2923, 2924, producing forward trafficmessage signals 1, 2, . . . N. The power level of the forward APCsignal, the forward OW, and traffic message signals are adjusted by therespective amplifiers 2925, 2926 and 2927 to produce the power leveladjusted forward APC, OW and TRCH channels signals. These signals arecombined by the adder 2928 and applied to the VGA2 2914, which producesforward link RF channel signal.

The forward link RF channel signal including the spread forward APCsignal is received by the RF antenna of the SU, and demodulated toproduce the forward CDMA signal FMCH. This signal is provided to thevariable gain amplifier (VGA3) 2940. The output signal of VGA3 isapplied to the AGC 2941 which produces a variable gain amplifier controlsignal to VGA3 2940. This signal maintains the level of the outputsignal of VGA3 at a near constant level. The output signal of VGA3 2940is despread by the despread demux 2942, which produces a despread usermessage signal SUMS and a reverse APC bit. The reverse APC bit isapplied to the integrator 2943 which produces the reverse APC controlsignal. This reverse APC control signal is provided to the reverse APCVGA4 2944 to maintain the reverse link RF channel signal at a minimumpower level.

The despread user message signal SUMS is also applied to the powermeasurement circuit 2945 producing a power measurement signal, which isadded to the complement of threshold value S2 in the adder 2946 toproduce error signal ES3. The signal ES3 is an error signal relating tothe RCS transmit power level for the particular SU. To obtain thresholdS2, the noise power of a despread signal produced by the AUX despreader2985, as measured by the power measurement circuit 2986, is multipliedusing multiplier 2987 by 1 plus the desired signal to noise ratioSNR_(R). The AUX despreader 2985 despreads the output signal of VGA3using an uncorrelated spreading code, hence its output is an indicationof the despread noise power. Similarly, the control signal for the VGA3is applied to the rate scaling circuit 2970 to reduce the rate of thecontrol signal for VGA3 in order to produce a scaled received powerlevel RP1. The threshold compute circuit 2998 computes the receivedsignal threshold RST from the SU measured power signal SUUSR. Thecomplement of the scaled received power level RP1 and the receivedsignal threshold RST are applied to the adder 2994 which produces errorsignal ES4. This error is related to the RCS transmit power to all otherSUs. The input error signals ES3 and ES4 are combined in the combiner2999 and input to the delta modulator DM2 2947. The output signal of DM22947 is the forward APC bit stream signal, with bits having value ofvalue +1 or −1. In the exemplary embodiment of the present invention,this signal is transmitted as a 64 kb/s signal.

The forward APC bit stream signal is applied to the spreading circuit2948, to produce the output reverse spread-spectrum APC signal. ReverseOW and traffic signals are also input to spreading circuits 2949, 2950,producing reverse OW and traffic message signals 1, 2, . . . N, and thereverse pilot is generated by the reverse pilot generator 2951. Thepower level of the reverse APC message signal, reverse OW messagesignal, reverse pilot, and the reverse traffic message signals areadjusted by amplifiers 2952, 2953, 2954, 2955 to produce the signalswhich are combined by the adder 2956 and input to the reverse APC VGA42944. It is this VGA4 2944 which produces the reverse link RF channelsignal.

During the call connection and bearer channel establishment process, theclosed loop power control of the present invention is modified, and isshown in FIGS. 30A and 30B. As shown, the circuits used to adjust thetransmitted power are different for the RCS, shown as the initial RCSpower control module 3001; and for the SU, shown as the initial SU powercontrol module 3002. Beginning with the initial RCS power control module3001, the reverse link RF channel signal is received at the RF antennaand demodulated producing the reverse CDMA signal IRMCH which isreceived by the first variable gain amplifier (VGA1) 3003. The outputsignal of VGA1 is detected by the AGC circuit (AGC1) 3004 which providesa variable gain amplifier control signal to VGA1 3003 to maintain thelevel of the output signal of VGA1 at a near constant value. The outputsignal of VGA1 is despread by the despread demultiplexer 3005, whichproduces a despread user message signal IMS. The forward APC controlsignal, ISET, is set to a fixed value, and is applied to the forwardlink variable gain amplifier (VGA2) 3006 to set the forward link RFchannel signal at a predetermined level.

The signal power of the despread user message signal IMS of the InitialRCS power module 3001 is measured by the power measure circuit 3007, andthe output power measurement is subtracted from a threshold value S3 inthe subtracter 3008 to produce error signal ES5, which is an errorsignal relating to the transmit power level of a particular SU. Thethreshold S3 is calculated by multiplying using a multiplier 3083 thedespread power measurement by measure power 3082 obtained from the AUXdespreader 3081 by 1 plus the desired signal to noise ratio SNR_(R). TheAUX despreader 3081 despreads the signal using an uncorrelated spreadingcode, hence its output signal is an indication of despread noise power.Similarly, the VGA1 control signal is applied to the rate scalingcircuit 3009 to reduce the rate of the VGA1 control signal in order toproduce a scaled system power level signal SP2. The thresholdcomputation logic 3010 determines an initial system signal thresholdvalue (ISST) computed from the user channel power data signal (IRCSUSR).The complement of the scaled system power level signal SP2 and the ISSTare provided to the adder 3011 which produces a second error signal ES6,which is an error signal relating to the system transmit power level ofall active SUs. The value of ISST is the desired transmit power for asystem having the particular configuration. The input error signals ES5and ES6 are combined in the combiner 3012 to produce a combined errorsignal input to the delta modulator (DM3) 3013. DM3 produces the initialreverse APC bit stream signal, having bits of value +1 or −1, which inthe exemplary embodiment is transmitted as a 64 kb/s signal.

The reverse APC bit stream signal is applied to the spreading circuit3014, to produce the initial spread-spectrum forward APC signal. TheCTCH information is spread by the spreader 3016 to form the spread CTCHmessage signal. The spread APC and CTCH signals are scaled by theamplifiers 3015 and 3017, and combined by the combiner 3018. Thecombined signal is applied to VGA2 3006, which produces the forward linkRF channel signal.

The forward link RF channel signal including the spread forward APCsignal is received by the RF antenna of the SU and demodulated toproduce the initial forward CDMA signal (IFMCH) which is applied to thevariable gain amplifier (VGA3) 3020. The output signal of VGA3 isdetected by the AGC circuit (AGC2) 3021 which produces a variable gainamplifier control signal for the VGA3 3020. This signal maintains theoutput power level of the VGA3 3020 at a near constant value. The outputsignal of VGA3 is despread by the despread demultiplexer 3022, whichproduces an initial reverse APC bit that is dependent on the outputlevel of VGA3. The reverse APC bit is processed by the integrator 3023to produce the reverse APC control signal. The reverse APC controlsignal is provided to the reverse APC VGA4 3024 to maintain the reverselink RF channel signal at a defined power level.

The global channel AXCH signal is spread by the spreading circuits 3025to provide the spread AXCH channel signal. The reverse pilot generator3026 provides a reverse pilot signal, and the signal power of AXCH andthe reverse pilot signal are adjusted by the respective amplifiers 3027and 3028. The spread AXCH channel signal and the reverse pilot signalare summed by the adder 3029 to produce reverse link CDMA signal. Thereverse link CDMA signal is received by the reverse APC VGA4 3024, whichproduces the reverse link RF channel signal output to the RFtransmitter.

XXXX. System Capacity Management

The system capacity management algorithm of the present inventionoptimizes the maximum user capacity for an RCS area, called a cell. Whenthe SU comes within a certain value of maximum transmit power, the SUsends an alarm message to the RCS. The RCS sets the traffic lights whichcontrol access to the system to “red” which, as previously described, isa flag that inhibits access by the SU's. This condition remains ineffect until the call to the alarming SU terminates, or until thetransmit power of the alarming SU, measured at the SU, is a value lessthan the maximum transmit power. When multiple SUs send alarm messages,the condition remains in effect until either all calls from alarming SUsterminate or until the transmit power of the alarming SU, measured atthe SU, is less than the maximum transmit power. An alternativeembodiment monitors the bit error rate measurements from the FECdecoder, and holds the RCS traffic lights at “red” until the bit errorrate is less than a predetermined value.

The blocking strategy of the present invention includes a method whichuses the power control information transmitted from the RCS to an SU,and the received power measurements at the RCS. The RCS measures itstransmit power level, detects that a maximum value is reached anddetermines when to block new users. An SU preparing to enter the systemblocks itself if the SU reaches the maximum transmit power beforesuccessful completion of a bearer channel assignment.

Each additional user in the system has the effect of increasing thenoise level for all other users, which decreases the signal to noiseratio (SNR) that each user experiences. The power control algorithmmaintains a desired SNR for each user. Therefore, in the absence of anyother limitations, addition of a new user into the system has only atransient effect and the desired SNR is regained.

The transmit power measurement at the RCS is done by measuring eitherthe root mean square (rms) value of the baseband combined signal or bymeasuring the transmit power of the RF signal and feeding it back todigital control circuits. The transmit power measurement may also bemade by the SUs to determine if the unit has reached its maximumtransmit power. The SU transmit power level is determined by measuringthe control signal of the RF amplifier, and scaling the value based onthe service type, such as POTS, FAX, or ISDN.

The information that an SU has reached the maximum power is transmittedto the RCS by the SU in a message on the assigned channels. The RCS alsodetermines the condition by measuring reverse APC changes because, ifthe RCS sends APC messages to the SU to increase SU transmit power, andthe SU transmit power measured at the RCS is not increased, the SU hasreached the maximum transmit power.

The RCS does not use traffic lights to block new users who have finishedramping-up using the short codes. These users are blocked by denyingthem the dial tone and letting them time out. The RCS sends all 1's (godown commands) on the APC channel to make the SU lower its transmitpower. The RCS also sends either no CTCH message or a message with aninvalid address which would force the FSU to abandon the accessprocedure and start over. The SU, however, does not start theacquisition process immediately because the traffic lights are red.

When the RCS reaches its transmit power limit, it enforces blocking inthe same manner as when an SU reaches its transmit power limit. The RCSturns off all the traffic lights on the FBCH, starts sending all 1 APCbits (go down commands) to those users who have completed their shortcode ramp-up but have not yet been given a dial tone, and either sendsno CTCH message to these users or sends messages with invalid addressesto force them to abandon the access process.

The self blocking process of the SU is as follows. When the SU startstransmitting the AXCH, the APC starts its power control operation usingthe AXCH and the SU transmit power increases. While the transmit poweris increasing under the control of the APC it is monitored by the SUcontroller. If the transmit power limit is reached, the SU abandons theaccess procedure and starts over.

XXXXI. System Synchronization

The RCS is synchronized either to the PSTN network clock signal throughone of the line interfaces, as shown in FIG. 10 or to the RCS systemclock oscillator, which free-runs to provide a master timing signal forthe system. The global pilot channel, and therefore all logical channelswithin the CDMA channel, are synchronized to the system clock signal ofthe RCS. The global pilot (GLPT) is transmitted by the RCS and definesthe timing at the RCS transmitter.

The SU receiver is synchronized to the GLPT, and so behaves as a slaveto the network clock oscillator. However, the SU timing is retarded bythe propagation delay. In the present embodiment of the invention, theSU modem extracts a 64 KHz and 8 KHz clock signal from the CDMA RFreceive channel, and a PLL oscillator circuit creates 2 MHz and 4 MHzclock signals

The SU transmitter and hence the LAXPT or ASPT are slaved to the timingof the SU receiver. The RCS receiver is synchronized to the LAXPT or theASPT transmitted by the SU, however, its timing may be retarded by thepropagation delay. Hence, the timing of the RCS receiver is that of theRCS transmitter retarded by twice the propagation delay.

Furthermore, the system can be synchronized via a reference receivedfrom a GPS receiver. In a system of this type, a GPS receiver in eachRCS provides a reference clock signal to all submodules of the RCS.Because each RCS receives the same time reference from the GPS, all ofthe system clock signals in all of the RCSs are synchronized.

Although the invention has been described in terms of multiple exemplaryembodiments, it is understood by those skilled in the art that theinvention may be practiced with modifications to the embodiments thatare within the scope of the invention as defined by the followingclaims.

1. A method for transmitting data from a base station to a subscriberunit in a code division multiple access communication system, the methodcomprising: producing a code, the code produced by binary addition of afirst sequence produced by a first feedback shift register with a secondsequence produced by a second feedback shift register; combining thecode with encoded message data, producing spread data; and transmittingthe spread data as a quadrature modulated signal.
 2. The method of clam1 wherein the quadrature modulated signal is a quadrature phase shiftkeying signal.
 3. The method of claim 1 wherein the encoded data isconvolutionally encoded data.
 4. The method of claim 1 furthercomprising transmitting a spread pilot channel, the spread pilot channelhaving a code produced by binary addition of a first sequence producedfrom the first feedback shift register with a second sequence producedby the second feedback shift register.
 5. The method of claim 1 whereinthe first feedback shift register is a linear feedback shift register.6. The method of claim 1 further comprising transmitting paginginformation on a broadcast channel, the broadcast channel having a codeproduced by binary addition of a first sequence produced from the firstfeedback shift register with a second sequence produced by the secondfeedback shift register.
 7. The method of claim 1 further comprisingtransmitting a spread pilot channel, the spread pilot channel producedby a linear feedback shift register circuit, the linear feedback shiftregister circuit having a total of thirty six stages.
 8. The method ofclaim 1 further comprising transmitting paging information on abroadcast channel, the broadcast channel having a code produced by alinear feedback shift register circuit, the linear feedback shiftregister circuit having a total of thirty six stages.